84 lines
3.1 KiB
C
84 lines
3.1 KiB
C
/*
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* intel_mid_hsi.h
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*
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* Header for the Intel HSI controller driver.
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*
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* Copyright (C) 2010, 2011 Intel Corporation. All rights reserved.
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*
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* Contact: Jim Stanley <jim.stanley@intel.com>
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* Olivier Stoltz Douchet <olivierx.stoltz-douchet@intel.com>
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* Faouaz TENOUTIT <faouazx.tenoutit@intel.com>
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*
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* Modified from OMAP SSI driver
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*/
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#ifndef __INTEL_MID_HSI_H__
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#define __INTEL_MID_HSI_H__
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#define HSI_PNW_PCI_DEVICE_ID 0x833 /* PCI id for Penwell HSI */
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#define HSI_CLV_PCI_DEVICE_ID 0x902 /* PCI id for Cloverview HSI */
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#define HSI_TNG_PCI_DEVICE_ID 0x1197 /* PCI id for Tangier HSI */
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#define HSI_PNW_MASTER_DMA_ID 0x834 /* PCI id for Penwell DWAHB dma */
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#define HSI_CLV_MASTER_DMA_ID 0x903 /* PCI id for Cloverview DWAHB dma */
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#define HSI_MID_MAX_CHANNELS 8
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/**
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* struct hsi_mid_platform_data - HSI platform specific data for clients
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* @rx_dma_channels: HSI-channel indexed list of RX DMA channel (-1 if no DMA)
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* @rx_sg_entries: HSI-channel indexed list of RX scatter gather entries
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* @rx_fifo_size: HSI-channel indexed list of RX FIFO size in HSI frames
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* @rx_fifo_thres: HSI-channel indexed list of RX FIFO threshold in HSI frames
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* @tx_dma_channels: HSI-channel indexed list of TX DMA channel (-1 if no DMA)
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* @tx_sg_entries: HSI-channel indexed list of TX scatter gather entries
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* @tx_fifo_size: HSI-channel indexed list of TX FIFO size in HSI frames
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* @tx_fifo_thres: HSI-channel indexed list of TX FIFO threshold in HSI frames
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* @tx_priorities: HSI-channel indexed list of TX priorities
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* @gpio_mdm_rst_out: GPIO index for modem reset input
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* @gpio_mdm_pwr_on: GPIO index for modem power on
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* @gpio_mdm_rst_bbn: GPIO index for modem reset request
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* @gpio_fcdp_rb: GPIO index for modem core dump
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*/
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struct hsi_mid_platform_data {
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int rx_dma_channels[HSI_MID_MAX_CHANNELS];
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int rx_sg_entries[HSI_MID_MAX_CHANNELS];
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int rx_fifo_sizes[HSI_MID_MAX_CHANNELS];
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int rx_fifo_thres[HSI_MID_MAX_CHANNELS];
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int tx_dma_channels[HSI_MID_MAX_CHANNELS];
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int tx_sg_entries[HSI_MID_MAX_CHANNELS];
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int tx_fifo_sizes[HSI_MID_MAX_CHANNELS];
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int tx_fifo_thres[HSI_MID_MAX_CHANNELS];
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int tx_priorities[HSI_MID_MAX_CHANNELS];
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/* FIXME: the next four entries need to go in a separate client specific
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* section */
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int gpio_mdm_rst_out;
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int gpio_mdm_pwr_on;
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int gpio_mdm_rst_bbn;
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int gpio_fcdp_rb;
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};
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struct hsi_mid_pci_platform_data {
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int gpio_wake;
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bool use_oob_cawake;
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};
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#endif /* __INTEL_MID_HSI_H__ */
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