263 lines
7.4 KiB
C
263 lines
7.4 KiB
C
/*
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* <Driver for I2S protocol on SSP (Moorestown and Medfield hardware)>
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* Copyright (c) 2010, Intel Corporation.
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* Louis LE GALL <louis.le.gall intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef MID_I2S_COMMON_H_
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#define MID_I2S_COMMON_H_
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#include <linux/types.h>
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/*
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* SSCR0 settings
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*/
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enum mrst_ssp_mode {
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SSP_IN_NORMAL_MODE = 0x0,
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SSP_IN_NETWORK_MODE,
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SSP_INVALID_MODE = 0xF
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};
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enum mrst_ssp_rx_fifo_over_run_int_mask {
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SSP_RX_FIFO_OVER_INT_ENABLE = 0x0,
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SSP_RX_FIFO_OVER_INT_DISABLE
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};
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enum mrst_ssp_tx_fifo_under_run_int_mask {
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SSP_TX_FIFO_UNDER_INT_ENABLE = 0x0,
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SSP_TX_FIFO_UNDER_INT_DISABLE
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};
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enum mrst_ssp_frame_format {
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MOTOROLA_SPI_FORMAT = 0x0,
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TI_SSP_FORMAT,
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MICROWIRE_FORMAT,
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PSP_FORMAT
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};
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enum mrst_ssp_master_mode_clock_selection {
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SSP_ONCHIP_CLOCK = 0x0,
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SSP_NETWORK_CLOCK,
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SSP_EXTERNAL_CLOCK,
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SSP_ONCHIP_AUDIO_CLOCK,
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SSP_MASTER_CLOCK_UNDEFINED = 0xFF
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};
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/*
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* Following enum and define are for frequency calculation in master mode...
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*/
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enum mrst_ssp_frm_freq {
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SSP_FRM_FREQ_UNDEFINED = 0,
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SSP_FRM_FREQ_48_000,
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SSP_FRM_FREQ_44_100,
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SSP_FRM_FREQ_22_050,
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SSP_FRM_FREQ_16_000,
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SSP_FRM_FREQ_11_025,
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SSP_FRM_FREQ_8_000,
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SSP_FRM_FREQ_SIZE
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};
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/*
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* SSCR1 settings
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*/
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enum mrst_ssp_txd_tristate_last_phase {
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TXD_TRISTATE_LAST_PHASE_OFF = 0x0,
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TXD_TRISTATE_LAST_PHASE_ON
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};
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enum mrst_ssp_txd_tristate_enable {
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TXD_TRISTATE_OFF = 0x0,
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TXD_TRISTATE_ON
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};
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enum mrst_ssp_slave_sspclk_free_running {
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SLAVE_SSPCLK_ON_ALWAYS = 0x0,
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SLAVE_SSPCLK_ON_DURING_TRANSFER_ONLY
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};
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enum mrst_ssp_sspsclk_direction {
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SSPSCLK_MASTER_MODE = 0x0,
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SSPSCLK_SLAVE_MODE
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};
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enum mrst_ssp_sspsfrm_direction {
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SSPSFRM_MASTER_MODE = 0x0,
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SSPSFRM_SLAVE_MODE
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};
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enum mrst_ssp_rx_without_tx {
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RX_AND_TX_MODE = 0x0,
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RX_WITHOUT_TX_MODE
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};
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enum mrst_trailing_byte_mode {
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SSP_TRAILING_BYTE_HDL_BY_IA = 0x0,
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SSP_TRAILING_BYTE_HDL_BY_DMA
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};
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enum mrst_ssp_tx_dma_status {
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SSP_TX_DMA_MASK = 0x0,
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SSP_TX_DMA_ENABLE
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};
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enum mrst_ssp_rx_dma_status {
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SSP_RX_DMA_MASK = 0x0,
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SSP_RX_DMA_ENABLE
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};
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enum mrst_ssp_rx_timeout_int_status {
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SSP_RX_TIMEOUT_INT_DISABLE = 0x0,
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SSP_RX_TIMEOUT_INT_ENABLE
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};
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enum mrst_ssp_trailing_byte_int_status {
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SSP_TRAILING_BYTE_INT_DISABLE = 0x0,
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SSP_TRAILING_BYTE_INT_ENABLE
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};
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enum mrst_ssp_loopback_mode_status {
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SSP_LOOPBACK_OFF = 0x0,
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SSP_LOOPBACK_ON
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};
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/*
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* SSPSP settings: for PSP Format ONLY!!!!!!!!
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*/
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enum mrst_ssp_frame_sync_relative_timing_bit {
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NEXT_FRMS_ASS_AFTER_END_OF_T4 = 0x0,
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NEXT_FRMS_ASS_WITH_LSB_PREVIOUS_FRM
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};
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enum mrst_ssp_frame_sync_polarity_bit {
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SSP_FRMS_ACTIVE_LOW = 0x0,
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SSP_FRMS_ACTIVE_HIGH
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};
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enum mrst_ssp_end_of_transfer_data_state {
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SSP_END_DATA_TRANSFER_STATE_LOW = 0x0,
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SSP_END_DATA_TRANSFER_STATE_PEVIOUS_BIT
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};
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enum mrst_ssp_clk_mode {
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SSP_CLK_MODE_0 = 0x0,
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SSP_CLK_MODE_1,
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SSP_CLK_MODE_2,
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SSP_CLK_MODE_3
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};
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#ifdef CONFIG_ACPI
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#define ACPI_FREQ_LEN 4
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struct intel_mid_i2s_ssp_config {
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__u8 ssp_psp_T1;
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__u8 ssp_psp_T2;
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__u8 ssp_psp_T4; /* DMYSTOP */
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__u8 ssp_psp_T5; /* SFRMDLY */
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__u8 ssp_psp_T6; /* SFRMWDTH */
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bool valid;
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};
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enum ssp_config_type {
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SSPCONF_NONE = 0,
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SSPCONF_PCM0,
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SSPCONF_PCM1,
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SSPCONF_I2S0
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};
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#define CONFIG_C08K "C08K"
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#define CONFIG_C16K "C16K"
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#define CONFIG_C48K "C48K"
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struct name_to_config_type {
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char config_name[ACPI_FREQ_LEN+1];
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enum ssp_config_type type;
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};
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#endif
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/*
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* Structure used to configure the SSP Port
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* Please note that only the PSP format and the DMA transfer are supported
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*
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* mode : Normal or Network (Network typically used in systems where
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* several devices are connected to same TX, RX, FRMS, CLK...
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* rx_fifo_interrupt : mask fifo over run interrupts.
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* tx_fifo_interrupt : mask fifo under run interrupts.
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* frame_format : 4 format available. PSP is Programmable Serial Protocol
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* master_mode_clk_selection : select which clock will be used to generate
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* the clock in master mode.
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* frame_rate_divider_control : number of time slots used in network mode.
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* however, this is second priority vs doing required framesync clock in
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* master mode (this number may be increased to reach correct framesync
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* rate). The active tx & rx slot map will be limit the real active slots.
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* master_mode_standard_freq : in master mode, select which standard frame
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* frequency you want to be generated by SSP.
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* data_size : size in bits of each sample. In master mode only 8, 16 or 32
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* data sizes are supported.
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* tx_tristate_phase : tri state phase (see langwell spec...)
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* tx_tristate_enable : enable tri state of tx when not transmitting data.
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*
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*/
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struct intel_mid_i2s_settings {
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enum mrst_ssp_mode mode;
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enum mrst_ssp_rx_fifo_over_run_int_mask rx_fifo_interrupt;
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enum mrst_ssp_tx_fifo_under_run_int_mask tx_fifo_interrupt;
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enum mrst_ssp_frame_format frame_format;
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/* below for Master Mode Only */
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enum mrst_ssp_master_mode_clock_selection master_mode_clk_selection;
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__u8 frame_rate_divider_control;
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/* below for Master Mode Only */
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enum mrst_ssp_frm_freq master_mode_standard_freq;
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__u16 data_size;
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enum mrst_ssp_txd_tristate_last_phase tx_tristate_phase;
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enum mrst_ssp_txd_tristate_enable tx_tristate_enable;
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enum mrst_ssp_slave_sspclk_free_running slave_clk_free_running_status;
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enum mrst_ssp_sspsclk_direction sspslclk_direction;
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enum mrst_ssp_sspsfrm_direction sspsfrm_direction;
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enum mrst_ssp_rx_without_tx ssp_duplex_mode;
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enum mrst_trailing_byte_mode ssp_trailing_byte_mode;
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enum mrst_ssp_tx_dma_status ssp_tx_dma;
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enum mrst_ssp_rx_dma_status ssp_rx_dma;
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enum mrst_ssp_rx_timeout_int_status
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ssp_rx_timeout_interrupt_status;
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enum mrst_ssp_trailing_byte_int_status
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ssp_trailing_byte_interrupt_status;
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enum mrst_ssp_loopback_mode_status ssp_loopback_mode_status;
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__u8 ssp_rx_fifo_threshold;
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__u8 ssp_tx_fifo_threshold;
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enum mrst_ssp_frame_sync_relative_timing_bit ssp_frmsync_timing_bit;
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enum mrst_ssp_frame_sync_polarity_bit ssp_frmsync_pol_bit;
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enum mrst_ssp_end_of_transfer_data_state ssp_end_transfer_state;
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enum mrst_ssp_clk_mode ssp_serial_clk_mode;
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__u8 ssp_psp_T1;
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__u8 ssp_psp_T2;
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__u8 ssp_psp_T4; /* DMYSTOP */
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__u8 ssp_psp_T5; /* SFRMDLY */
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__u8 ssp_psp_T6; /* SFRMWDTH */
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__u8 ssp_active_tx_slots_map;
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__u8 ssp_active_rx_slots_map;
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};
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#endif /* MID_I2S_COMMON_H_*/
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