529 lines
15 KiB
C
529 lines
15 KiB
C
/* ***********************************************************************************************
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2013 Intel Corporation. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution
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in the file called LICENSE.GPL.
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Contact Information:
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SOCWatch Developer Team <socwatchdevelopers@intel.com>
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BSD LICENSE
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Copyright(c) 2013 Intel Corporation. All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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***********************************************************************************************
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*/
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#ifndef _MATRIXIO_H_
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#define _MATRIXIO_H_
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#include "pw_version.h"
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#include "pw_defines.h"
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// #define MATRIX_IO_FILE "/dev/matrix"
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#define SOCWATCH_DRIVER_NAME_ICS "socwatch"
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#define SOCWATCH_DRIVER_NAME SOCWATCH_DRIVER_NAME_ICS
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#define SOCWATCH_DRIVER_NAME_WITH_PATH_ICS "/dev/socwatch"
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#define SOCWATCH_DRIVER_NAME_WITH_PATH SOCWATCH_DRIVER_NAME_WITH_PATH_ICS
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// #define MATRIX_IO_FILE "/dev/matrix_ICS"
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#define SOCWATCH_IO_FILE SOCWATCH_DRIVER_NAME_WITH_PATH_ICS
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/*enumerate operations to be done in an IOCTL scan(init, poll & term) */
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enum IOCtlType {
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READ_OP = 0x00000001,
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WRITE_OP = 0x00000002,
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ENABLE_OP = 0x00000004,
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SET_BITS_OP = 0x00000040,
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RESET_BITS_OP = 0x00000080,
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};
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#define MAX_GMCH_CTRL_REGS 4
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#define MAX_GMCH_DATA_REGS 8
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#define DATA_ENABLE 0x00000001
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#define MTX_GMCH_PMON_GLOBAL_CTRL 0x0005F1F0
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#define MTX_GMCH_PMON_GLOBAL_CTRL_ENABLE 0x0001000F
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#define MTX_GMCH_PMON_GLOBAL_CTRL_DISABLE 0x00000000
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#define MTX_GMCH_PMON_FIXED_CTR0 0x0005E8F0
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#define MTX_GMCH_PMON_GP_CTR0_L 0x0005F8F0
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#define MTX_GMCH_PMON_GP_CTR0_H 0x0005FCF0
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#define MTX_GMCH_PMON_GP_CTR1_L 0x0005F9F0
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#define MTX_GMCH_PMON_GP_CTR1_H 0x0005FDF0
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#define MTX_GMCH_PMON_GP_CTR2_L 0x0005FAF0
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#define MTX_GMCH_PMON_GP_CTR2_H 0x0005FEF0
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#define MTX_GMCH_PMON_GP_CTR3_L 0x0005FBF0
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#define MTX_GMCH_PMON_GP_CTR3_H 0x0005FFF0
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#define MTX_GMCH_PMON_FIXED_CTR_CTRL 0x0005F4F0
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#define MTX_PCI_MSG_CTRL_REG 0x000000D0
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#define MTX_PCI_MSG_DATA_REG 0x000000D4
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#define PWR_MGMT_BASE_ADDR_MASK 0xFFFF
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#define PWR_STS_NORTH_CMPLX_LOWER 0x4
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#define PWR_STS_NORTH_CMPLX_UPPER 0x30
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struct mtx_msr {
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unsigned long eax_LSB;
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unsigned long edx_MSB;
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unsigned long ecx_address;
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unsigned long ebx_value;
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unsigned long n_cpu;
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unsigned long operation;
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};
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struct memory_map {
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unsigned long ctrl_addr;
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void *ctrl_remap_address;
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unsigned long ctrl_data;
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unsigned long data_addr;
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void *data_remap_address;
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char *ptr_data_usr;
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unsigned long data_size;
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unsigned long operation;
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};
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struct mtx_pci_ops {
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unsigned long port;
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unsigned long data;
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unsigned long io_type;
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unsigned long port_island;
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};
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struct mtx_soc_perf {
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char *ptr_data_usr;
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unsigned long data_size;
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unsigned long operation;
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};
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/* PCI info for a real pci device */
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struct pci_config {
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unsigned long bus;
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unsigned long device;
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unsigned long function;
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unsigned long offset;
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unsigned long data; /* This is written to by the ioctl */
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};
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struct scu_config {
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unsigned long *address;
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unsigned char *usr_data;
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unsigned char *drv_data;
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unsigned long length;
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};
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struct lookup_table {
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/*Init Data */
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struct mtx_msr *msrs_init;
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unsigned long msr_init_length;
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unsigned long msr_init_wb;
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struct memory_map *mmap_init;
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unsigned long mem_init_length;
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unsigned long mem_init_wb;
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struct mtx_pci_ops *pci_ops_init;
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unsigned long pci_ops_init_length;
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unsigned long pci_ops_init_wb;
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unsigned long *cfg_db_init;
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unsigned long cfg_db_init_length;
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unsigned long cfg_db_init_wb;
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struct mtx_soc_perf *soc_perf_init;
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unsigned long soc_perf_init_length;
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unsigned long soc_perf_init_wb;
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/*Poll Data */
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struct mtx_msr *msrs_poll;
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unsigned long msr_poll_length;
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unsigned long msr_poll_wb;
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struct memory_map *mmap_poll;
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unsigned long mem_poll_length;
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unsigned long mem_poll_wb;
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unsigned long records;
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struct mtx_pci_ops *pci_ops_poll;
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unsigned long pci_ops_poll_length;
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unsigned long pci_ops_poll_wb;
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unsigned long pci_ops_records;
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unsigned long *cfg_db_poll;
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unsigned long cfg_db_poll_length;
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unsigned long cfg_db_poll_wb;
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struct scu_config scu_poll;
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unsigned long scu_poll_length;
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struct mtx_soc_perf *soc_perf_poll;
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unsigned long soc_perf_poll_length;
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unsigned long soc_perf_poll_wb;
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unsigned long soc_perf_records;
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/*Term Data */
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struct mtx_msr *msrs_term;
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unsigned long msr_term_length;
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unsigned long msr_term_wb;
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struct memory_map *mmap_term;
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unsigned long mem_term_length;
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unsigned long mem_term_wb;
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struct mtx_pci_ops *pci_ops_term;
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unsigned long pci_ops_term_length;
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unsigned long pci_ops_term_wb;
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unsigned long *cfg_db_term;
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unsigned long cfg_db_term_length;
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unsigned long cfg_db_term_wb;
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struct mtx_soc_perf *soc_perf_term;
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unsigned long soc_perf_term_length;
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unsigned long soc_perf_term_wb;
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};
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/*
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* 32b support in 64b kernel space
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*/
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#if defined (__linux__)
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#ifdef __KERNEL__
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#if defined(HAVE_COMPAT_IOCTL) && defined(CONFIG_X86_64)
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#include <linux/compat.h>
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// #include <asm/compat.h>
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struct mtx_msr32 {
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compat_ulong_t eax_LSB;
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compat_ulong_t edx_MSB;
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compat_ulong_t ecx_address;
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compat_ulong_t ebx_value;
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compat_ulong_t n_cpu;
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compat_ulong_t operation;
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};
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struct memory_map32 {
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compat_ulong_t ctrl_addr;
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compat_caddr_t ctrl_remap_address;
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compat_ulong_t ctrl_data;
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compat_ulong_t data_addr;
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compat_caddr_t data_remap_address;
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compat_caddr_t ptr_data_usr;
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compat_ulong_t data_size;
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compat_ulong_t operation;
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};
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struct mtx_pci_ops32 {
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compat_ulong_t port;
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compat_ulong_t data;
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compat_ulong_t io_type;
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compat_ulong_t port_island;
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};
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struct mtx_soc_perf32 {
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compat_caddr_t ptr_data_usr;
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compat_ulong_t data_size;
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compat_ulong_t operation;
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};
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struct pci_config32 {
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compat_ulong_t bus;
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compat_ulong_t device;
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compat_ulong_t function;
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compat_ulong_t offset;
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compat_ulong_t data; /* This is written to by the ioctl */
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};
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struct scu_config32 {
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compat_caddr_t address;
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compat_caddr_t usr_data;
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compat_caddr_t drv_data;
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compat_ulong_t length;
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};
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struct lookup_table32 {
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/*Init Data */
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compat_caddr_t msrs_init;
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compat_ulong_t msr_init_length;
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compat_ulong_t msr_init_wb;
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compat_caddr_t mmap_init;
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compat_ulong_t mem_init_length;
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compat_ulong_t mem_init_wb;
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compat_caddr_t pci_ops_init;
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compat_ulong_t pci_ops_init_length;
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compat_ulong_t pci_ops_init_wb;
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compat_caddr_t cfg_db_init;
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compat_ulong_t cfg_db_init_length;
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compat_ulong_t cfg_db_init_wb;
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compat_caddr_t soc_perf_init;
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compat_ulong_t soc_perf_init_length;
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compat_ulong_t soc_perf_init_wb;
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/*Poll Data */
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compat_caddr_t msrs_poll;
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compat_ulong_t msr_poll_length;
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compat_ulong_t msr_poll_wb;
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compat_caddr_t mmap_poll;
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compat_ulong_t mem_poll_length;
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compat_ulong_t mem_poll_wb;
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compat_ulong_t records;
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compat_caddr_t pci_ops_poll;
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compat_ulong_t pci_ops_poll_length;
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compat_ulong_t pci_ops_poll_wb;
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compat_ulong_t pci_ops_records;
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compat_caddr_t cfg_db_poll;
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compat_ulong_t cfg_db_poll_length;
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compat_ulong_t cfg_db_poll_wb;
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struct scu_config32 scu_poll;
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compat_ulong_t scu_poll_length;
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compat_caddr_t soc_perf_poll;
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compat_ulong_t soc_perf_poll_length;
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compat_ulong_t soc_perf_poll_wb;
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compat_ulong_t soc_perf_records;
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/*Term Data */
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compat_caddr_t msrs_term;
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compat_ulong_t msr_term_length;
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compat_ulong_t msr_term_wb;
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compat_caddr_t mmap_term;
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compat_ulong_t mem_term_length;
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compat_ulong_t mem_term_wb;
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compat_caddr_t pci_ops_term;
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compat_ulong_t pci_ops_term_length;
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compat_ulong_t pci_ops_term_wb;
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compat_caddr_t cfg_db_term;
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compat_ulong_t cfg_db_term_length;
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compat_ulong_t cfg_db_term_wb;
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compat_caddr_t soc_perf_term;
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compat_ulong_t soc_perf_term_length;
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compat_ulong_t soc_perf_term_wb;
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};
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struct mtx_msr_container32 {
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compat_caddr_t buffer;
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compat_ulong_t length;
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struct mtx_msr32 msrType1;
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};
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#endif // HAVE_COMPAT_IOCTL && CONFIG_X86_64
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#endif // __KERNEL__
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#endif // __linux__
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struct msr_buffer {
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unsigned long eax_LSB;
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unsigned long edx_MSB;
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};
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struct mt_msr_buffer {
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u32 eax_LSB;
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u32 edx_MSB;
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};
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#define MAX_SOC_PERF_VALUES 10
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struct soc_perf_buffer {
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unsigned long long values[MAX_SOC_PERF_VALUES];
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};
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struct mt_soc_perf_buffer {
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u64 values[MAX_SOC_PERF_VALUES];
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};
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struct xchange_buffer {
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struct msr_buffer *ptr_msr_buff;
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unsigned long msr_length;
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unsigned long *ptr_mem_buff;
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unsigned long mem_length;
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unsigned long *ptr_pci_ops_buff;
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unsigned long pci_ops_length;
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unsigned long *ptr_cfg_db_buff;
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unsigned long cfg_db_length;
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struct soc_perf_buffer *ptr_soc_perf_buff;
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unsigned long soc_perf_length;
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};
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struct mt_xchange_buffer {
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u64 ptr_msr_buff;
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u64 ptr_mem_buff;
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u64 ptr_pci_ops_buff;
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u64 ptr_cfg_db_buff;
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u64 ptr_soc_perf_buff;
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u32 msr_length;
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u32 mem_length;
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u32 pci_ops_length;
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u32 cfg_db_length;
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u32 soc_perf_length;
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u32 padding; // Required to keep sizeof(mt_xchange_buffer) the same on 32b and 64b systems
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// in the absence of #pragma pack(XXX) directives!
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};
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struct xchange_buffer_all {
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unsigned long long init_time_stamp;
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unsigned long long *poll_time_stamp;
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unsigned long long term_time_stamp;
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unsigned long long init_tsc;
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unsigned long long term_tsc;
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unsigned long long *poll_tsc;
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struct xchange_buffer xhg_buf_init;
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struct xchange_buffer xhg_buf_poll;
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struct xchange_buffer xhg_buf_term;
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unsigned long status;
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};
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struct mtx_msr_container {
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unsigned long *buffer;
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unsigned long length;
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struct mtx_msr msrType1;
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};
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struct gmch_container {
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unsigned long long time_stamp;
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unsigned long read_mask;
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unsigned long write_mask;
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unsigned long mcr1[MAX_GMCH_CTRL_REGS];
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unsigned long mcr2[MAX_GMCH_CTRL_REGS];
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unsigned long mcr3[MAX_GMCH_CTRL_REGS];
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unsigned long data[MAX_GMCH_DATA_REGS];
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unsigned long event[MAX_GMCH_CTRL_REGS];
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unsigned long core_clks;
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};
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struct mtx_size_info {
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unsigned int init_msr_size;
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unsigned int term_msr_size;
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unsigned int poll_msr_size;
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unsigned int init_mem_size;
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unsigned int term_mem_size;
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unsigned int poll_mem_size;
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unsigned int init_pci_ops_size;
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unsigned int term_pci_ops_size;
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unsigned int poll_pci_ops_size;
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unsigned int init_cfg_db_size;
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unsigned int term_cfg_db_size;
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unsigned int poll_cfg_db_size;
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unsigned int poll_scu_drv_size;
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unsigned int total_mem_bytes_req;
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unsigned int init_soc_perf_size;
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unsigned int term_soc_perf_size;
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unsigned int poll_soc_perf_size;
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};
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#define IOCTL_INIT_SCAN _IOR(0xF8, 0x00000001, unsigned long)
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#define IOCTL_TERM_SCAN _IOR(0xF8, 0x00000002, unsigned long)
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#define IOCTL_POLL_SCAN _IOR(0xF8, 0x00000004, unsigned long)
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#define IOCTL_INIT_MEMORY _IOR(0xF8, 0x00000010, struct xchange_buffer_all *)
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#define IOCTL_FREE_MEMORY _IO(0xF8, 0x00000020)
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#define IOCTL_READ_PCI_CONFIG _IOWR(0xF8, 0x00000001, struct pci_config *)
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#define IOCTL_VERSION_INFO _IOW(0xF8, 0x00000001, char *)
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#define IOCTL_COPY_TO_USER _IOW(0xF8, 0x00000002, struct xchange_buffer_all *)
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#define IOCTL_READ_CONFIG_DB _IOW(0xF8, 0x00000004, unsigned long *)
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#define IOCTL_WRITE_CONFIG_DB _IOW(0xF8, 0x00000010, unsigned long *)
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#define IOCTL_OPERATE_ON_MSR _IOW(0xF8, 0x00000020, struct mtx_msr *)
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#define IOCTL_MSR _IOW(0xF8, 0x00000040, struct mtx_msr_container *)
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#define IOCTL_SRAM _IOW(0xF8, 0x00000080, struct memory_map *)
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#define IOCTL_GMCH_RESET _IOW(0xF8, 0x00000003, struct gmch_container *)
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#define IOCTL_GMCH _IOW(0xF8, 0x00000005, struct gmch_container *)
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#define IOCTL_GET_SOC_STEPPING _IOR(0xF8, 0x00000100, unsigned long *)
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#define IOCTL_GET_SCU_FW_VERSION _IOR(0xF8, 0x00000200, unsigned long *)
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#define IOCTL_GET_DRIVER_VERSION _IOW(0xF8, 0x00000400, unsigned long *)
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#if defined (__linux__)
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#ifdef __KERNEL__
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#if defined(HAVE_COMPAT_IOCTL) && defined(CONFIG_X86_64)
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#define IOCTL_INIT_SCAN32 _IOR(0xF8, 0x00000001, compat_ulong_t)
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#define IOCTL_TERM_SCAN32 _IOR(0xF8, 0x00000002, compat_ulong_t)
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#define IOCTL_POLL_SCAN32 _IOR(0xF8, 0x00000004, compat_ulong_t)
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#define IOCTL_INIT_MEMORY32 _IOR(0xF8, 0x00000010, compat_uptr_t)
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#define IOCTL_FREE_MEMORY32 _IO(0xF8, 0x00000020)
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#define IOCTL_READ_PCI_CONFIG32 _IOWR(0xF8, 0x00000001, compat_uptr_t)
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#define IOCTL_VERSION_INFO32 _IOW(0xF8, 0x00000001, compat_caddr_t)
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#define IOCTL_COPY_TO_USER32 _IOW(0xF8, 0x00000002, compat_uptr_t)
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#define IOCTL_READ_CONFIG_DB32 _IOW(0xF8, 0x00000004, compat_uptr_t)
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#define IOCTL_WRITE_CONFIG_DB32 _IOW(0xF8, 0x00000010, compat_uptr_t)
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#define IOCTL_OPERATE_ON_MSR32 _IOW(0xF8, 0x00000020, compat_uptr_t)
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#define IOCTL_MSR32 _IOW(0xF8, 0x00000040, compat_uptr_t)
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#define IOCTL_SRAM32 _IOW(0xF8, 0x00000080, compat_uptr_t)
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#define IOCTL_GMCH_RESET32 _IOW(0xF8, 0x00000003, compat_uptr_t)
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#define IOCTL_GMCH32 _IOW(0xF8, 0x00000005, compat_uptr_t)
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#define IOCTL_GET_SOC_STEPPING32 _IOR(0xF8, 0x00000100, compat_uptr_t)
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#define IOCTL_GET_SCU_FW_VERSION32 _IOR(0xF8, 0x00000200, compat_uptr_t)
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#define IOCTL_GET_DRIVER_VERSION32 _IOW(0xF8, 0x00000400, compat_uptr_t)
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#endif // HAVE_COMPAT_IOCTL && CONFIG_X86_64
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#endif // __KERNEL__
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#endif // __linux__
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#define platform_pci_read32 intel_mid_msgbus_read32_raw
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#define platform_pci_write32 intel_mid_msgbus_write32_raw
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#endif
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