267 lines
12 KiB
C
267 lines
12 KiB
C
/*COPYRIGHT**
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* -------------------------------------------------------------------------
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* INTEL CORPORATION PROPRIETARY INFORMATION
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* This software is supplied under the terms of the accompanying license
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* agreement or nondisclosure agreement with Intel Corporation and may not
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* be copied or disclosed except in accordance with the terms of that
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* agreement.
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* Copyright (C) 2007-2014 Intel Corporation. All Rights Reserved.
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* -------------------------------------------------------------------------
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**COPYRIGHT*/
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#ifndef _LWPMUDRV_CHIPSET_H_
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#define _LWPMUDRV_CHIPSET_H_
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define MAX_CHIPSET_EVENT_NAME 64
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#define MAX_CHIPSET_COUNTERS 5 // TODO: this covers 1 fixed counter
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// plus 4 general counters on GMCH;
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// for other chipset devices, this
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// can vary from 8 to 32; might consider
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// making this per-chipset-type since
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// event-multiplexing is currently not
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// supported for chipset collections
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#if defined(_NTDDK_)
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#define CHIPSET_PHYS_ADDRESS PHYSICAL_ADDRESS
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#else
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#define CHIPSET_PHYS_ADDRESS U64
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#endif
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// possible values for whether chipset data is valid or not
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enum {
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DATA_IS_VALID,
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DATA_IS_INVALID,
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DATA_OUT_OF_RANGE
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};
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typedef struct CHIPSET_EVENT_NODE_S CHIPSET_EVENT_NODE;
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typedef CHIPSET_EVENT_NODE *CHIPSET_EVENT;
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//chipset event
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struct CHIPSET_EVENT_NODE_S {
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U32 event_id;
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U32 group_id;
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char name[MAX_CHIPSET_EVENT_NAME];
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U32 pm;
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U32 counter;
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};
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#define CHIPSET_EVENT_event_id(chipset_event) (chipset_event)->event_id
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#define CHIPSET_EVENT_group_id(chipset_event) (chipset_event)->group_id
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#define CHIPSET_EVENT_name(chipset_event) (chipset_event)->name
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#define CHIPSET_EVENT_pm(chipset_event) (chipset_event)->pm
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#define CHIPSET_EVENT_counter(chipset_event) (chipset_event)->counter
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typedef struct CHIPSET_SEGMENT_NODE_S CHIPSET_SEGMENT_NODE;
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typedef CHIPSET_SEGMENT_NODE *CHIPSET_SEGMENT;
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//chipset segment data
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struct CHIPSET_SEGMENT_NODE_S {
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CHIPSET_PHYS_ADDRESS physical_address;
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U64 virtual_address;
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U16 size;
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U16 number_of_counters;
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U16 total_events;
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U16 start_register; // (see driver for details)
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U32 read_register; // read register offset (model dependent)
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U32 write_register; // write register offset (model dependent)
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CHIPSET_EVENT_NODE events[MAX_CHIPSET_COUNTERS];
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};
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#define CHIPSET_SEGMENT_physical_address(chipset_segment) (chipset_segment)->physical_address
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#define CHIPSET_SEGMENT_virtual_address(chipset_segment) (chipset_segment)->virtual_address
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#define CHIPSET_SEGMENT_size(chipset_segment) (chipset_segment)->size
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#define CHIPSET_SEGMENT_num_counters(chipset_segment) (chipset_segment)->number_of_counters
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#define CHIPSET_SEGMENT_total_events(chipset_segment) (chipset_segment)->total_events
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#define CHIPSET_SEGMENT_start_register(chipset_segment) (chipset_segment)->start_register
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#define CHIPSET_SEGMENT_read_register(chipset_segment) (chipset_segment)->read_register
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#define CHIPSET_SEGMENT_write_register(chipset_segment) (chipset_segment)->write_register
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#define CHIPSET_SEGMENT_events(chipset_segment) (chipset_segment)->events
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typedef struct CHIPSET_CONFIG_NODE_S CHIPSET_CONFIG_NODE;
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typedef CHIPSET_CONFIG_NODE *CHIPSET_CONFIG;
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//chipset struct used for communication between user mode and kernel
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struct CHIPSET_CONFIG_NODE_S
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{
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U32 length; // length of this entire area
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U32 major_version;
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U32 minor_version;
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U32 rsvd;
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U64 cpu_counter_mask;
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struct {
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U64 processor : 1; // Processor PMU
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U64 mch_chipset : 1; // MCH Chipset
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U64 ich_chipset : 1; // ICH Chipset
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U64 motherboard_time_flag : 1; // Motherboard_Time requested.
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U64 host_processor_run : 1; // Each processor should manage the MCH counts they see.
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// Turn off for Gen 4 (NOA) runs.
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U64 mmio_noa_registers : 1; // NOA
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U64 bnb_chipset : 1; // BNB Chipset
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U64 gmch_chipset : 1; // GMCH Chipset
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U64 rsvd : 56;
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} config_flags;
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CHIPSET_SEGMENT_NODE mch;
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CHIPSET_SEGMENT_NODE ich;
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CHIPSET_SEGMENT_NODE mmio;
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CHIPSET_SEGMENT_NODE bnb;
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CHIPSET_SEGMENT_NODE gmch;
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};
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#define CHIPSET_CONFIG_length(chipset) (chipset)->length
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#define CHIPSET_CONFIG_major_version(chipset) (chipset)->major_version
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#define CHIPSET_CONFIG_minor_version(chipset) (chipset)->minor_version
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#define CHIPSET_CONFIG_cpu_counter_mask(chipset) (chipset)->cpu_counter_mask
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#define CHIPSET_CONFIG_processor(chipset) (chipset)->config_flags.processor
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#define CHIPSET_CONFIG_mch_chipset(chipset) (chipset)->config_flags.mch_chipset
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#define CHIPSET_CONFIG_ich_chipset(chipset) (chipset)->config_flags.ich_chipset
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#define CHIPSET_CONFIG_motherboard_time(chipset) (chipset)->config_flags.motherboard_time_flag
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#define CHIPSET_CONFIG_host_proc_run(chipset) (chipset)->config_flags.host_processor_run
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#define CHIPSET_CONFIG_noa_chipset(chipset) (chipset)->config_flags.mmio_noa_registers
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#define CHIPSET_CONFIG_bnb_chipset(chipset) (chipset)->config_flags.bnb_chipset
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#define CHIPSET_CONFIG_gmch_chipset(chipset) (chipset)->config_flags.gmch_chipset
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#define CHIPSET_CONFIG_mch(chipset) (chipset)->mch
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#define CHIPSET_CONFIG_ich(chipset) (chipset)->ich
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#define CHIPSET_CONFIG_noa(chipset) (chipset)->mmio
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#define CHIPSET_CONFIG_bnb(chipset) (chipset)->bnb
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#define CHIPSET_CONFIG_gmch(chipset) (chipset)->gmch
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typedef struct CHIPSET_PCI_ARG_NODE_S CHIPSET_PCI_ARG_NODE;
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typedef CHIPSET_PCI_ARG_NODE *CHIPSET_PCI_ARG;
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struct CHIPSET_PCI_ARG_NODE_S {
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U32 address;
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U32 value;
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};
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#define CHIPSET_PCI_ARG_address(chipset_pci) (chipset_pci)->address
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#define CHIPSET_PCI_ARG_value(chipset_pci) (chipset_pci)->value
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typedef struct CHIPSET_PCI_SEARCH_ADDR_NODE_S CHIPSET_PCI_SEARCH_ADDR_NODE;
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typedef CHIPSET_PCI_SEARCH_ADDR_NODE *CHIPSET_PCI_SEARCH_ADDR;
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struct CHIPSET_PCI_SEARCH_ADDR_NODE_S {
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U32 start;
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U32 stop;
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U32 increment;
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U32 addr;
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};
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#define CHIPSET_PCI_SEARCH_ADDR_start(pci_search_addr) (pci_search_addr)->start
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#define CHIPSET_PCI_SEARCH_ADDR_stop(pci_search_addr) (pci_search_addr)->stop
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#define CHIPSET_PCI_SEARCH_ADDR_increment(pci_search_addr) (pci_search_addr)->increment
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#define CHIPSET_PCI_SEARCH_ADDR_address(pci_search_addr) (pci_search_addr)->addr
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typedef struct CHIPSET_PCI_CONFIG_NODE_S CHIPSET_PCI_CONFIG_NODE;
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typedef CHIPSET_PCI_CONFIG_NODE *CHIPSET_PCI_CONFIG;
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struct CHIPSET_PCI_CONFIG_NODE_S
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{
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U32 bus;
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U32 device;
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U32 function;
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U32 offset;
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U32 value;
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};
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#define CHIPSET_PCI_CONFIG_bus(pci_config) (pci_config)->bus
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#define CHIPSET_PCI_CONFIG_device(pci_config) (pci_config)->device
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#define CHIPSET_PCI_CONFIG_function(pci_config) (pci_config)->function
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#define CHIPSET_PCI_CONFIG_offset(pci_config) (pci_config)->offset
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#define CHIPSET_PCI_CONFIG_value(pci_config) (pci_config)->value
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typedef struct CHIPSET_MARKER_NODE_S CHIPSET_MARKER_NODE;
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typedef CHIPSET_MARKER_NODE *CHIPSET_MARKER;
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struct CHIPSET_MARKER_NODE_S {
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U32 processor_number;
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U32 rsvd;
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U64 tsc;
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};
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#define CHIPSET_MARKER_processor_number(chipset_marker) (pci_config)->processor_number
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#define CHIPSET_MARKER_tsc(chipset_marker) (pci_config)->tsc
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typedef struct CHAP_INTERFACE_NODE_S CHAP_INTERFACE_NODE;
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typedef CHAP_INTERFACE_NODE *CHAP_INTERFACE;
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// CHAP chipset registers
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// The offsets for registers are command-0x00, event-0x04, status-0x08, data-0x0C
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struct CHAP_INTERFACE_NODE_S {
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U32 command_register;
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U32 event_register;
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U32 status_register;
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U32 data_register;
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};
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#define CHAP_INTERFACE_command_register(chap) (chap)->command_register
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#define CHAP_INTERFACE_event_register(chap) (chap)->event_register
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#define CHAP_INTERFACE_status_register(chap) (chap)->status_register
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#define CHAP_INTERFACE_data_register(chap) (chap)->data_register
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/**************************************************************************
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* GMCH Registers and Offsets
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**************************************************************************
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*/
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// Counter registers - each counter has 4 registers
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#define GMCH_MSG_CTRL_REG 0xD0 // message control register (MCR) 0xD0-0xD3
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#define GMCH_MSG_DATA_REG 0xD4 // message data register (MDR) 0xD4-0xD7
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// Counter register offsets
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#define GMCH_PMON_CAPABILITIES 0x0005F0F0 // when read, bit 0 enabled means GMCH counters are available
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#define GMCH_PMON_GLOBAL_CTRL 0x0005F1F0 // simultaneously enables or disables fixed and general counters
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// Fixed counters (32-bit)
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#define GMCH_PMON_FIXED_CTR_CTRL 0x0005F4F0 // enables and filters the fixed counters
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#define GMCH_PMON_FIXED_CTR0 0x0005E8F0 // 32-bit fixed counter for GMCH_CORE_CLKS event
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#define GMCH_PMON_FIXED_CTR_OVF_VAL 0xFFFFFFFFLL // overflow value for GMCH fixed counters
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// General counters (38-bit)
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// NOTE: lower order bits on GP counters must be read before the higher bits!
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#define GMCH_PMON_GP_CTR0_L 0x0005F8F0 // GMCH GP counter 0, low bits
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#define GMCH_PMON_GP_CTR0_H 0x0005FCF0 // GMCH GP counter 0, high bits
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#define GMCH_PMON_GP_CTR1_L 0x0005F9F0
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#define GMCH_PMON_GP_CTR1_H 0x0005FDF0
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#define GMCH_PMON_GP_CTR2_L 0x0005FAF0
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#define GMCH_PMON_GP_CTR2_H 0x0005FEF0
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#define GMCH_PMON_GP_CTR3_L 0x0005FBF0
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#define GMCH_PMON_GP_CTR3_H 0x0005FFF0
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#define GMCH_PMON_GP_CTR_OVF_VAL 0x3FFFFFFFFFLL // overflow value for GMCH general counters
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/* other counter register offsets ...
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#define GMCH_PMON_GLOBAL_STATUS 0x0005F2F0 // bit 16 indicates overflow on fixed counter 0; bits 0-3 indicate overflows on GP counters 0-3
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#define GMCH_PMON_GLOBAL_OVF_CTRL 0x0005F3F0 // on CDV, it is write-only psuedo-register that always returns 0 when read
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#define GMCH_PMON_PERFEVTSEL0 0x0005E0F0 // this is used for selecting which event in GP counter 0 to count
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#define GMCH_PMON_PERFEVTSEL1 0x0005E1F0 // this is used for selecting which event in GP counter 1 to count
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#define GMCH_PMON_PERFEVTSEL2 0x0005E2F0 // this is used for selecting which event in GP counter 2 to count
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#define GMCH_PMON_PERFEVTSEL3 0x0005E3F0 // this is used for selecting which event in GP counter 3 to count
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#define GMCH_PERF_ADDR_LIMIT_H 0x0001E8F0 // used for qualifying upper address limit for DRAM_PAGE_STATUS event
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#define GMCH_PERF_ADDR_LIMIT_L 0x0001E9F0 // used for qualifying lower address limit for DRAM_PAGE_STATUS event
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#define GMCH_PERF_BANK_SEL 0x0001EAF0 // used for addtional qualification of DRAM_PAGE_STATUS event
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*/
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// Register offsets for LNC
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#define LNC_GMCH_REGISTER_READ 0xD0000000
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#define LNC_GMCH_REGISTER_WRITE 0xE0000000
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// Register offsets for SLT
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#define SLT_GMCH_REGISTER_READ 0x10000000
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#define SLT_GMCH_REGISTER_WRITE 0x11000000
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// Register offsets for CDV
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#define CDV_GMCH_REGISTER_READ 0x10000000
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#define CDV_GMCH_REGISTER_WRITE 0x11000000
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#if defined(__cplusplus)
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}
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#endif
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#endif
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