128 lines
4.0 KiB
C
128 lines
4.0 KiB
C
/*
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Copyright (C) 2005-2014 Intel Corporation. All Rights Reserved.
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This file is part of SEP Development Kit
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SEP Development Kit is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation.
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SEP Development Kit is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with SEP Development Kit; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software
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library without restriction. Specifically, if other files instantiate
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templates or use macros or inline functions from this file, or you compile
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this file and link it with other files to produce an executable, this
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file does not by itself cause the resulting executable to be covered by
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the GNU General Public License. This exception does not however
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invalidate any other reasons why the executable file might be covered by
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the GNU General Public License.
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*/
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#ifndef _APIC_H_
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#define _APIC_H_
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#include <stddef.h>
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#include <linux/irq.h>
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typedef U64 *PHYSICAL_ADDRESS;
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/**
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// Data Types and Macros
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*/
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/*
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// APIC registers and constants
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*/
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// APIC base MSR
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#define DRV_APIC_BASE_MSR 0x001b
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// APIC registers
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#define DRV_APIC_LCL_ID 0x0020
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#define DRV_APIC_LCL_TSKPRI 0x0080
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#define DRV_APIC_LCL_PPR 0x00a0
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#define DRV_APIC_LCL_EOI 0x00b0
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#define DRV_APIC_LCL_LDEST 0x00d0
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#define DRV_APIC_LCL_DSTFMT 0x00e0
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#define DRV_APIC_LCL_SVR 0x00f0
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#define DRV_APIC_LCL_ICR 0x0300
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#define DRV_APIC_LVT_TIMER 0x0320
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#define DRV_APIC_LVT_PMI 0x0340
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#define DRV_APIC_LVT_LINT0 0x0350
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#define DRV_APIC_LVT_LINT1 0x0360
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#define DRV_APIC_LVT_ERROR 0x0370
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#define DRV_APIC_LCL_ID_MSR 0x802
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#define DRV_APIC_LCL_TSKPRI_MSR 0x808
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#define DRV_APIC_LCL_PPR_MSR 0x80a
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#define DRV_APIC_LCL_EOI_MSR 0x80b
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#define DRV_APIC_LCL_LDEST_MSR 0x80d
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#define DRV_APIC_LCL_DSTFMT_MSR 0x80e
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#define DRV_APIC_LCL_SVR_MSR 0x80f
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#define DRV_APIC_LCL_ICR_MSR 0x830
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#define DRV_APIC_LVT_TIMER_MSR 0x832
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#define DRV_APIC_LVT_PMI_MSR 0x834
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#define DRV_APIC_LVT_LINT0_MSR 0x835
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#define DRV_APIC_LVT_LINT1_MSR 0x836
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#define DRV_APIC_LVT_ERROR_MSR 0x837
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// masks for LVT
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#define DRV_LVT_MASK 0x10000
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#define DRV_LVT_EDGE 0x00000
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#define DRV_LVT_LEVEL 0x08000
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#define DRV_LVT_EXTINT 0x00700
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#define DRV_LVT_NMI 0x00400
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// task priorities
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#define DRV_APIC_TSKPRI_LO 0x0000
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#define DRV_APIC_TSKPRI_HI 0x00f0
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#define DRV_X2APIC_ENABLED 0xc00LL
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//// Interrupt vector for PMU overflow event
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//
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// Choose the highest unused IDT vector possible so that our
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// callback routine runs at the highest priority allowed;
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// must avoid using pre-defined vectors in,
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// include/asm/irq.h
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// include/asm/hw_irq.h
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// include/asm/irq_vectors.h
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//
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// FIRST_DEVICE_VECTOR should be valid for kernels 2.6.33 and earlier
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#if defined(DRV_USE_NMI)
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#define CPU_PERF_VECTOR DRV_LVT_NMI
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#else
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#if defined(FIRST_DEVICE_VECTOR)
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#define CPU_PERF_VECTOR (FIRST_DEVICE_VECTOR - 1)
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// FIRST_EXTERNAL_VECTOR should be valid for kernels 2.6.34 and later
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#else
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#define CPU_PERF_VECTOR (FIRST_EXTERNAL_VECTOR + 1)
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#endif
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#endif
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// Has the APIC Been enabled
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#define DRV_APIC_BASE_GLOBAL_ENABLED(a) ((a) & 1 << 11)
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#define DRV_APIC_VIRTUAL_WIRE_ENABLED(a) ((a) & 0x100)
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extern U32 drv_x2apic_enabled;
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/**
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// Function Declarations
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*/
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/*
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// APIC control functions
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*/
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extern VOID APIC_Disable_PMI(VOID);
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extern VOID APIC_Deinit_Phase1(int cpu_idx);
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extern VOID APIC_Ack_Eoi(VOID);
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extern VOID APIC_Enable_Pmi(VOID);
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extern VOID APIC_Init(PVOID param);
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extern VOID APIC_Install_Interrupt_Handler(PVOID param);
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extern VOID APIC_Unmap(PVOID addr);
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#endif
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