164 lines
4.2 KiB
C
164 lines
4.2 KiB
C
/*COPYRIGHT**
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Copyright (C) 2011-2014 Intel Corporation. All Rights Reserved.
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This file is part of SEP Development Kit
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SEP Development Kit is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation.
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SEP Development Kit is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with SEP Development Kit; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software
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library without restriction. Specifically, if other files instantiate
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templates or use macros or inline functions from this file, or you compile
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this file and link it with other files to produce an executable, this
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file does not by itself cause the resulting executable to be covered by
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the GNU General Public License. This exception does not however
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invalidate any other reasons why the executable file might be covered by
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the GNU General Public License.
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**COPYRIGHT*/
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#include "lwpmudrv_defines.h"
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#include <linux/version.h>
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#include <linux/wait.h>
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#include <linux/fs.h>
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#include "lwpmudrv_types.h"
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#include "rise_errors.h"
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#include "lwpmudrv_ecb.h"
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#include "lwpmudrv_struct.h"
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#include "lwpmudrv.h"
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#include "utility.h"
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#include "control.h"
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#include "output.h"
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#include "hsw_unc_ncu.h"
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#include "ecb_iterators.h"
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#include "pebs.h"
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#include "unc_common.h"
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extern U64 *read_unc_ctr_info;
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static VOID inline
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unc_ncu_Enable_PMU(
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VOID *param,
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U32 control_msr
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)
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{
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ECB pecb_unc;
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U32 dev_idx = *((U32*)param);
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pecb_unc = LWPMU_DEVICE_PMU_register_data(&devices[dev_idx])[0];
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if (GLOBAL_STATE_current_phase(driver_state) == DRV_STATE_RUNNING) {
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SYS_Write_MSR(control_msr, ECB_entries_reg_value(pecb_unc,0));
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}
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}
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/*!
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* @fn static VOID unc_ncu_hsw_Write_PMU(VOID*)
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*
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* @brief Initial write of PMU registers
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* Walk through the enties and write the value of the register accordingly.
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* When current_group = 0, then this is the first time this routine is called,
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*
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* @param None
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*
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* @return None
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*
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* <I>Special Notes:</I>
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*/
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static VOID
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unc_ncu_hsw_Write_PMU (
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VOID *param
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)
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{
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UNC_COMMON_MSR_Write_PMU(param,
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HSW_NCU_PERF_GLOBAL_CTRL,
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0,
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0,
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NULL);
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return;
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}
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/*!
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* @fn static VOID unc_ncu_hsw_Disable_PMU(PVOID)
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*
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* @brief Zero out the global control register. This automatically disables the
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* PMU counters.
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*
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* @param None
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*
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* @return None
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*
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* <I>Special Notes:</I>
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*/
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static VOID
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unc_ncu_hsw_Disable_PMU (
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PVOID param
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)
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{
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SYS_Write_MSR(HSW_NCU_PERF_GLOBAL_CTRL, 0LL);
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return;
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}
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/*!
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* @fn static VOID unc_ncu_hsw_Enable_PMU(PVOID)
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*
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* @brief Set the enable bit for all the CCCR registers
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*
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* @param param - device index
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*
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* @return None
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*
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* <I>Special Notes:</I>
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*/
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static VOID
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unc_ncu_hsw_Enable_PMU (
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PVOID param
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)
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{
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unc_ncu_Enable_PMU(param, HSW_NCU_PERF_GLOBAL_CTRL);
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return;
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}
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/*
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* Initialize the dispatch table
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*/
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DISPATCH_NODE haswellunc_ncu_dispatch =
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{
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NULL, // initialize
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NULL, // destroy
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unc_ncu_hsw_Write_PMU, // write
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unc_ncu_hsw_Disable_PMU, // freeze
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unc_ncu_hsw_Enable_PMU, // restart
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UNC_COMMON_MSR_Read_PMU_Data, // read
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NULL, // check for overflow
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NULL,
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NULL,
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UNC_COMMON_MSR_Clean_Up,
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NULL,
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NULL,
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NULL,
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UNC_COMMON_MSR_Read_Counts,
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NULL, // check_overflow_gp_errata
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NULL, // read_ro
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NULL, // platform_info
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NULL,
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NULL // scan for uncore
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};
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