303 lines
9.4 KiB
C
303 lines
9.4 KiB
C
#ifndef __M1120_H__
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#define __M1120_H__
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#include <linux/ioctl.h>
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#include <linux/mutex.h>
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/* ********************************************************* */
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/* feature of ic revision */
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/* ********************************************************* */
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#define M1120_REV_0_2 (0x02)
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#define M1120_REV_1_0 (0x10)
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#define M1120_REV M1120_REV_1_0
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#define M1120_DRIVER_VERSION "Ver1.04-140226"
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/* ********************************************************* */
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/* ********************************************************* */
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/* property of driver */
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/* ********************************************************* */
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#define M1120_DRIVER_NAME "m1120"
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#define M1120_IRQ_NAME "m1120-irq"
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#define M1120_PATH "/dev/m1120"
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#define M1120_SLAVE_ADDR (0x18)
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/* ********************************************************* */
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/* ********************************************************* */
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/* register map */
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/* ********************************************************* */
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#define M1120_REG_PERSINT (0x00)
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#define M1120_VAL_PERSINT_COUNT(n) (n<<4)
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#define M1120_VAL_PERSINT_INTCLR (0x01)
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/*
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[7:4] PERS : interrupt persistence count
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[0] INTCLR = 1 : interrupt clear
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_INTSRS (0x01)
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#define M1120_VAL_INTSRS_INT_ON (0x80)
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#define M1120_DETECTION_MODE_INTERRUPT M1120_VAL_INTSRS_INT_ON
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#define M1120_VAL_INTSRS_INT_OFF (0x00)
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#define M1120_DETECTION_MODE_POLLING M1120_VAL_INTSRS_INT_OFF
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#define M1120_VAL_INTSRS_INTTYPE_BESIDE (0x00)
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#define M1120_VAL_INTSRS_INTTYPE_WITHIN (0x40)
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#define M1120_VAL_INTSRS_SRS_10BIT_0_068mT (0x00)
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#define M1120_VAL_INTSRS_SRS_10BIT_0_034mT (0x01)
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#define M1120_VAL_INTSRS_SRS_10BIT_0_017mT (0x02)
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#define M1120_VAL_INTSRS_SRS_10BIT_0_009mT (0x03)
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#define M1120_VAL_INTSRS_SRS_10BIT_0_004mT (0x04)
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#define M1120_VAL_INTSRS_SRS_8BIT_0_272mT (0x00)
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#define M1120_VAL_INTSRS_SRS_8BIT_0_136mT (0x01)
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#define M1120_VAL_INTSRS_SRS_8BIT_0_068mT (0x02)
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#define M1120_VAL_INTSRS_SRS_8BIT_0_036mT (0x03)
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#define M1120_VAL_INTSRS_SRS_8BIT_0_016mT (0x04)
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/*
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[7] INTON = 0 : disable interrupt
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[7] INTON = 1 : enable interrupt
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[4] INT_TYP = 0 : generate inteerupt when raw data is within range of threshold
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[4] INT_TYP = 1 : generate interrupt when raw data is beside range of threshold
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[2:0] SRS : select sensitivity type when M1120_VAL_OPF_BIT_10
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000 : 0.068 (mT/LSB)
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001 : 0.034 (mT/LSB)
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010 : 0.017 (mT/LSB)
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011 : 0.009 (mT/LSB)
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100 : 0.004 (mT/LSB)
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101 : 0.017 (mT/LSB)
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110 : 0.017 (mT/LSB)
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111 : 0.017 (mT/LSB)
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[2:0] SRS : select sensitivity type when M1120_VAL_OPF_BIT_8
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000 : 0.272 (mT/LSB)
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001 : 0.136 (mT/LSB)
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010 : 0.068 (mT/LSB)
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011 : 0.036 (mT/LSB)
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100 : 0.016 (mT/LSB)
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101 : 0.068 (mT/LSB)
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110 : 0.068 (mT/LSB)
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111 : 0.068 (mT/LSB)
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_LTHL (0x02)
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/*
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[7:0] LTHL : low byte of low threshold value
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_LTHH (0x03)
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/*
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[7:6] LTHH : high 2bits of low threshold value with sign
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_HTHL (0x04)
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/*
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[7:0] HTHL : low byte of high threshold value
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_HTHH (0x05)
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/*
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[7:6] HTHH : high 2bits of high threshold value with sign
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_I2CDIS (0x06)
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#define M1120_VAL_I2CDISABLE (0x37)
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/*
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[7:0] I2CDIS : disable i2c
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_SRST (0x07)
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#define M1120_VAL_SRST_RESET (0x01)
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/*
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[0] SRST = 1 : soft reset
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_OPF (0x08)
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#define M1120_VAL_OPF_FREQ_20HZ (0x00)
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#define M1120_VAL_OPF_FREQ_10HZ (0x10)
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#define M1120_VAL_OPF_FREQ_6_7HZ (0x20)
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#define M1120_VAL_OPF_FREQ_5HZ (0x30)
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#define M1120_VAL_OPF_FREQ_80HZ (0x40)
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#define M1120_VAL_OPF_FREQ_40HZ (0x50)
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#define M1120_VAL_OPF_FREQ_26_7HZ (0x60)
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#define M1120_VAL_OPF_EFRD_ON (0x08)
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#define M1120_VAL_OPF_BIT_8 (0x02)
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#define M1120_VAL_OPF_BIT_10 (0x00)
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#define M1120_VAL_OPF_HSSON_ON (0x01)
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/*
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[6:4] OPF : operation frequency
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000 : 20 (Hz)
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001 : 10 (Hz)
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010 : 6.7 (Hz)
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011 : 5 (Hz)
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100 : 80 (Hz)
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101 : 40 (Hz)
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110 : 26.7 (Hz)
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111 : 20 (Hz)
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[3] EFRD = 0 : keep data without accessing eFuse
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[3] EFRD = 1 : update data after accessing eFuse
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[1] BIT = 0 : 10 bit resolution
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[1] BIT = 1 : 8 bit resolution
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[0] HSSON = 0 : Off power down mode
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[0] HSSON = 1 : On power down mode
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_DID (0x09)
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#define M1120_VAL_DID (0x9C)
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/*
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[7:0] DID : Device ID
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_INFO (0x0A)
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/*
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[7:0] INFO : Information about IC
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_ASA (0x0B)
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/*
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[7:0] ASA : Hall Sensor sensitivity adjustment
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_ST1 (0x10)
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#define M1120_VAL_ST1_DRDY (0x01)
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/*
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[4] INTM : status of interrupt mode
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[1] BITM : status of resolution
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[0] DRDY : status of data ready
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_HSL (0x11)
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/*
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[7:0] HSL : low byte of hall sensor measurement data
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*/
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/* --------------------------------------------------------- */
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#define M1120_REG_HSH (0x12)
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/*
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[7:6] HSL : high 2bits of hall sensor measurement data with sign
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*/
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/* ********************************************************* */
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/* ********************************************************* */
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/* ********************************************************* */
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/* ioctl command */
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/* ********************************************************* */
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#define M1120_IOCTL_BASE (0x80)
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#define M1120_IOCTL_SET_ENABLE _IOW(M1120_IOCTL_BASE, 0x00, int)
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#define M1120_IOCTL_GET_ENABLE _IOR(M1120_IOCTL_BASE, 0x01, int)
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#define M1120_IOCTL_SET_DELAY _IOW(M1120_IOCTL_BASE, 0x02, int)
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#define M1120_IOCTL_GET_DELAY _IOR(M1120_IOCTL_BASE, 0x03, int)
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#define M1120_IOCTL_SET_CALIBRATION _IOW(M1120_IOCTL_BASE, 0x04, int*)
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#define M1120_IOCTL_GET_CALIBRATED_DATA _IOR(M1120_IOCTL_BASE, 0x05, int*)
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#define M1120_IOCTL_SET_INTERRUPT _IOW(M1120_IOCTL_BASE, 0x06, unsigned int)
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#define M1120_IOCTL_GET_INTERRUPT _IOR(M1120_IOCTL_BASE, 0x07, unsigned int*)
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#define M1120_IOCTL_SET_THRESHOLD_HIGH _IOW(M1120_IOCTL_BASE, 0x08, unsigned int)
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#define M1120_IOCTL_GET_THRESHOLD_HIGH _IOR(M1120_IOCTL_BASE, 0x09, unsigned int*)
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#define M1120_IOCTL_SET_THRESHOLD_LOW _IOW(M1120_IOCTL_BASE, 0x0A, unsigned int)
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#define M1120_IOCTL_GET_THRESHOLD_LOW _IOR(M1120_IOCTL_BASE, 0x0B, unsigned int*)
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#define M1120_IOCTL_SET_REG _IOW(M1120_IOCTL_BASE, 0x0C, int)
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#define M1120_IOCTL_GET_REG _IOR(M1120_IOCTL_BASE, 0x0D, int)
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/* ********************************************************* */
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/* ********************************************************* */
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/* event property */
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/* ********************************************************* */
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#define DEFAULT_EVENT_TYPE EV_ABS
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#define DEFAULT_EVENT_CODE ABS_X
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#define DEFAULT_EVENT_DATA_CAPABILITY_MIN (-32768)
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#define DEFAULT_EVENT_DATA_CAPABILITY_MAX (32767)
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/* ********************************************************* */
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/* delay property */
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/* ********************************************************* */
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#define M1120_DELAY_MAX (200) // ms
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#define M1120_DELAY_MIN (20) // ms
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#define M1120_DELAY_FOR_READY (10) // ms
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/* ********************************************************* */
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/* ********************************************************* */
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/* data type for driver */
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/* ********************************************************* */
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enum {
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OPERATION_MODE_POWERDOWN,
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OPERATION_MODE_MEASUREMENT,
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OPERATION_MODE_FUSEROMACCESS
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};
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#define M1120_REG_NUM (15)
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typedef union {
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struct {
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unsigned char persint;
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unsigned char intsrs;
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unsigned char lthl;
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unsigned char lthh;
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unsigned char hthl;
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unsigned char hthh;
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unsigned char i2cdis;
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unsigned char srst;
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unsigned char opf;
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unsigned char did;
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unsigned char info;
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unsigned char asa;
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unsigned char st1;
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unsigned char hsl;
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unsigned char hsh;
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} map;
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unsigned char array[M1120_REG_NUM];
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} m1120_reg_t;
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typedef struct {
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struct mutex enable;
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struct mutex data;
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} m1120_mutex_t;
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typedef struct {
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atomic_t enable;
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atomic_t delay;
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atomic_t debug;
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} m1120_atomic_t;
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typedef struct {
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int power_vi2c;
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int power_vdd;
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int interrupt_gpio;
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int interrupt_irq;
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} m1120_platform_data_t;
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typedef struct {
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int type;
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int min;
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int max;
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} m1120_sts_cfg_t;
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typedef struct {
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struct i2c_client *client;
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struct input_dev *input_dev;
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m1120_mutex_t mtx;
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m1120_atomic_t atm;
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m1120_reg_t reg;
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bool irq_enabled;
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int calibrated_data;
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int last_data;
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short thrhigh;
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short thrlow;
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bool irq_first;
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struct delayed_work work;
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int power_vi2c;
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int power_vdd;
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int igpio;
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int irq;
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m1120_sts_cfg_t stscfg[7];
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int stscfg_init;
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} m1120_data_t;
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/* ********************************************************* */
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#endif // __M1120_H__
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