534 lines
11 KiB
C
534 lines
11 KiB
C
/*
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* Crystal Cove -- Device access for Intel PMIC for VLV2
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*
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* Copyright (c) 2013, Intel Corporation.
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*
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* Author: Yang Bin <bin.yang@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mfd/core.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/workqueue.h>
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#include <linux/mfd/intel_mid_pmic.h>
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#include <linux/acpi.h>
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#include <asm/intel_vlv2.h>
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#include <linux/version.h>
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#define PMIC_IRQ_NUM 7
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#define CHIPID 0x00
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#define CHIPVER 0x01
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#define IRQLVL1 0x02
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#define MIRQLVL1 0x0E
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enum {
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PWRSRC_IRQ = 0,
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THRM_IRQ,
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BCU_IRQ,
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ADC_IRQ,
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CHGR_IRQ,
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GPIO_IRQ,
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VHDMIOCP_IRQ
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};
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struct intel_mid_pmic {
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struct i2c_client *i2c;
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struct mutex io_lock;
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struct device *dev;
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int irq;
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struct mutex irq_lock;
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int irq_base;
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unsigned long irq_mask;
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struct workqueue_struct *workqueue;
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struct work_struct work;
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};
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static struct device *gpio_dev;
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static struct resource gpio_resources[] = {
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{
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.name = "GPIO",
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.start = GPIO_IRQ,
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.end = GPIO_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource pwrsrc_resources[] = {
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{
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.name = "PWRSRC",
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.start = PWRSRC_IRQ,
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.end = PWRSRC_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource adc_resources[] = {
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{
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.name = "ADC",
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.start = ADC_IRQ,
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.end = ADC_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource thermal_resources[] = {
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{
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.name = "THERMAL",
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.start = THRM_IRQ,
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.end = THRM_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource bcu_resources[] = {
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{
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.name = "BCU",
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.start = BCU_IRQ,
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.end = BCU_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mfd_cell crystal_cove_data[] = {
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{
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.name = "crystal_cove_pwrsrc",
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.id = 0,
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.num_resources = ARRAY_SIZE(pwrsrc_resources),
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.resources = pwrsrc_resources,
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},
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{
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.name = "crystal_cove_adc",
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.id = 0,
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "crystal_cove_thermal",
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.id = 0,
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "crystal_cove_bcu",
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.id = 0,
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "crystal_cove_gpio",
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.id = 0,
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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.platform_data = &gpio_dev,
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.pdata_size = sizeof(gpio_dev),
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},
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{NULL, },
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};
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int intel_mid_pmic_set_pdata(const char *name, void *data, int len)
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{
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int i;
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struct mfd_cell *cell;
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for (i = 0; i < ARRAY_SIZE(crystal_cove_data); i++) {
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cell = &crystal_cove_data[i];
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if (!strcmp(cell->name, name)) {
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cell->platform_data = data;
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cell->pdata_size = len;
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return 0;
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}
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}
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return -EINVAL;
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}
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EXPORT_SYMBOL(intel_mid_pmic_set_pdata);
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/* wrapper function needed by Baytrail BCU driver */
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int intel_scu_ipc_read_mip(u8 *data, int len, int offset, int issigned)
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{
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return 0;
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}
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EXPORT_SYMBOL(intel_scu_ipc_read_mip);
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static struct intel_mid_pmic intel_mid_pmic;
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static struct intel_mid_pmic *pmic = &intel_mid_pmic;
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/* These intel_scu_ipc_* APIs are formed to
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* be compatible with old SCU IPC APIs.
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*/
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int intel_scu_ipc_ioread8(u16 addr, u8 *data)
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{
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int ret;
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ret = intel_mid_pmic_readb(addr);
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if (ret < 0)
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return ret;
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*data = ret;
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return 0;
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}
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EXPORT_SYMBOL(intel_scu_ipc_ioread8);
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int intel_scu_ipc_iowrite8(u16 addr, u8 data)
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{
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return intel_mid_pmic_writeb(addr, data);
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}
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EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
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int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask)
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{
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int ret;
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if (!pmic->i2c)
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return -ENODEV;
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mutex_lock(&pmic->io_lock);
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ret = i2c_smbus_read_byte_data(pmic->i2c, addr);
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if (ret < 0)
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goto err;
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data &= mask;
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ret &= ~mask;
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ret |= data;
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ret = i2c_smbus_write_byte_data(pmic->i2c, addr, ret);
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err:
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mutex_unlock(&pmic->io_lock);
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return ret;
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}
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EXPORT_SYMBOL(intel_scu_ipc_update_register);
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int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
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{
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int i;
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int ret;
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if (len < 1 || len > 4)
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return -EINVAL;
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for (i = 0; i < len; i++) {
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ret = intel_scu_ipc_ioread8(addr[i], &data[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL(intel_scu_ipc_readv);
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int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
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{
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int i;
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int ret;
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if (len < 1 || len > 4)
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return -EINVAL;
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for (i = 0; i < len; i++) {
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ret = intel_scu_ipc_iowrite8(addr[i], data[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL(intel_scu_ipc_writev);
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int intel_mid_pmic_readb(int reg)
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{
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int ret;
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if (!pmic->i2c)
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return -ENODEV;
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mutex_lock(&pmic->io_lock);
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ret = i2c_smbus_read_byte_data(pmic->i2c, reg);
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mutex_unlock(&pmic->io_lock);
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return ret;
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}
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EXPORT_SYMBOL(intel_mid_pmic_readb);
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int intel_mid_pmic_writeb(int reg, u8 val)
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{
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int ret;
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if (!pmic->i2c)
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return -ENODEV;
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mutex_lock(&pmic->io_lock);
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ret = i2c_smbus_write_byte_data(pmic->i2c, reg, val);
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mutex_unlock(&pmic->io_lock);
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return ret;
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}
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EXPORT_SYMBOL(intel_mid_pmic_writeb);
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int intel_mid_pmic_setb(int reg, u8 mask)
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{
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int ret;
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int val;
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if (!pmic->i2c)
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return -ENODEV;
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mutex_lock(&pmic->io_lock);
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val = i2c_smbus_read_byte_data(pmic->i2c, reg);
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val |= mask;
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ret = i2c_smbus_write_byte_data(pmic->i2c, reg, val);
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mutex_unlock(&pmic->io_lock);
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return ret;
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}
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int intel_mid_pmic_clearb(int reg, u8 mask)
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{
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int ret;
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int val;
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if (!pmic->i2c)
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return -ENODEV;
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mutex_lock(&pmic->io_lock);
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val = i2c_smbus_read_byte_data(pmic->i2c, reg);
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val &= ~mask;
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ret = i2c_smbus_write_byte_data(pmic->i2c, reg, val);
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mutex_unlock(&pmic->io_lock);
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return ret;
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}
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static void pmic_irq_enable(struct irq_data *data)
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{
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clear_bit(data->irq - pmic->irq_base, &pmic->irq_mask);
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queue_work(pmic->workqueue, &pmic->work);
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}
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static void pmic_irq_disable(struct irq_data *data)
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{
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set_bit(data->irq - pmic->irq_base, &pmic->irq_mask);
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queue_work(pmic->workqueue, &pmic->work);
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}
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static void pmic_irq_sync_unlock(struct irq_data *data)
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{
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mutex_unlock(&pmic->irq_lock);
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}
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static void pmic_irq_lock(struct irq_data *data)
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{
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mutex_lock(&pmic->irq_lock);
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}
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static void pmic_work(struct work_struct *work)
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{
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mutex_lock(&pmic->irq_lock);
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intel_mid_pmic_writeb(MIRQLVL1, (u8)pmic->irq_mask);
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mutex_unlock(&pmic->irq_lock);
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}
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static irqreturn_t pmic_irq_isr(int irq, void *data)
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{
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return IRQ_WAKE_THREAD;
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}
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static irqreturn_t pmic_irq_thread(int irq, void *data)
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{
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int i;
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int pending;
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mutex_lock(&pmic->irq_lock);
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intel_mid_pmic_writeb(MIRQLVL1, (u8)pmic->irq_mask);
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pending = intel_mid_pmic_readb(IRQLVL1) & (~pmic->irq_mask);
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for (i = 0; i < PMIC_IRQ_NUM; i++)
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if (pending & (1 << i))
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handle_nested_irq(pmic->irq_base + i);
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mutex_unlock(&pmic->irq_lock);
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return IRQ_HANDLED;
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}
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static struct irq_chip pmic_irq_chip = {
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.name = "intel_mid_pmic",
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.irq_bus_lock = pmic_irq_lock,
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.irq_bus_sync_unlock = pmic_irq_sync_unlock,
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.irq_disable = pmic_irq_disable,
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.irq_enable = pmic_irq_enable,
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};
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static void pmic_shutdown(struct i2c_client *client)
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{
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dev_dbg(&client->dev, "%s called\n", __func__);
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if (pmic->irq > 0)
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disable_irq(pmic->irq);
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return;
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}
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static int pmic_suspend(struct device *dev)
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{
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dev_dbg(dev, "%s called\n", __func__);
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if (pmic->irq > 0)
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disable_irq(pmic->irq);
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return 0;
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}
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static int pmic_resume(struct device *dev)
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{
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dev_dbg(dev, "%s called\n", __func__);
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if (pmic->irq > 0)
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enable_irq(pmic->irq);
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return 0;
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}
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static const struct dev_pm_ops pmic_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pmic_suspend,
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pmic_resume)
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};
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static int pmic_irq_init(void)
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{
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int cur_irq;
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int ret;
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pmic->irq_mask = 0xff;
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ret = intel_mid_pmic_writeb(MIRQLVL1, pmic->irq_mask);
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if (ret) {
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dev_err(pmic->dev, "Failed to communicate with PMIC.");
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return ret;
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}
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pmic->irq_mask = intel_mid_pmic_readb(MIRQLVL1);
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pmic->irq_base = irq_alloc_descs(VV_PMIC_IRQBASE, 0, PMIC_IRQ_NUM, 0);
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if (pmic->irq_base < 0) {
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dev_warn(pmic->dev, "Failed to allocate IRQs: %d\n",
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pmic->irq_base);
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pmic->irq_base = 0;
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return -EINVAL;
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}
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/* Register them with genirq */
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for (cur_irq = pmic->irq_base;
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cur_irq < PMIC_IRQ_NUM + pmic->irq_base;
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cur_irq++) {
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irq_set_chip_data(cur_irq, pmic);
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irq_set_chip_and_handler(cur_irq, &pmic_irq_chip,
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handle_edge_irq);
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irq_set_nested_thread(cur_irq, 1);
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irq_set_noprobe(cur_irq);
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}
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ret = request_threaded_irq(pmic->irq, pmic_irq_isr, pmic_irq_thread,
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IRQF_TRIGGER_RISING | IRQF_ONESHOT,
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"intel_mid_pmic", pmic);
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if (ret != 0) {
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dev_err(pmic->dev, "Failed to request IRQ %d: %d\n",
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pmic->irq, ret);
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return ret;
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}
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ret = enable_irq_wake(pmic->irq);
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if (ret != 0) {
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dev_warn(pmic->dev, "Can't enable PMIC IRQ as wake source: %d\n",
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ret);
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}
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return 0;
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}
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static int pmic_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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int i, ret;
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struct mfd_cell *cell_dev = crystal_cove_data;
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mutex_init(&pmic->io_lock);
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mutex_init(&pmic->irq_lock);
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pmic->workqueue =
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create_singlethread_workqueue("crystal cove");
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INIT_WORK(&pmic->work, pmic_work);
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gpio_dev = &i2c->dev;
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pmic->i2c = i2c;
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pmic->dev = &i2c->dev;
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pmic->irq = i2c->irq;
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ret = pmic_irq_init();
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if (ret)
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return ret;
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dev_info(&i2c->dev, "Crystal Cove: ID 0x%02X, VERSION 0x%02X\n",
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intel_mid_pmic_readb(CHIPID), intel_mid_pmic_readb(CHIPVER));
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for (i = 0; cell_dev[i].name != NULL; i++)
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;
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 1))
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return mfd_add_devices(pmic->dev, -1, cell_dev, i,
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NULL, pmic->irq_base, NULL);
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#else
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return mfd_add_devices(pmic->dev, -1, cell_dev, i,
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NULL, pmic->irq_base);
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#endif
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}
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static int pmic_i2c_remove(struct i2c_client *i2c)
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{
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mfd_remove_devices(pmic->dev);
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return 0;
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}
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static const struct i2c_device_id pmic_i2c_id[] = {
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{ "crystal_cove", },
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{ "INT33FD", },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, pmic_i2c_id);
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static struct acpi_device_id pmic_acpi_match[] = {
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{ "TEST0001", 0 },
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{ "INT33FD", 0 },
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{ },
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};
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MODULE_DEVICE_TABLE(acpi, pmic_acpi_match);
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static struct i2c_driver pmic_i2c_driver = {
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.driver = {
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.name = "intel_mid_i2c_pmic",
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.owner = THIS_MODULE,
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.pm = &pmic_pm_ops,
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.acpi_match_table = ACPI_PTR(pmic_acpi_match),
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},
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.probe = pmic_i2c_probe,
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.remove = pmic_i2c_remove,
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.id_table = pmic_i2c_id,
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.shutdown = pmic_shutdown,
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};
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static int __init pmic_i2c_init(void)
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{
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int ret;
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ret = i2c_add_driver(&pmic_i2c_driver);
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if (ret != 0)
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pr_err("Failed to register pmic I2C driver: %d\n", ret);
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return ret;
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}
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subsys_initcall(pmic_i2c_init);
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static void __exit pmic_i2c_exit(void)
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{
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i2c_del_driver(&pmic_i2c_driver);
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}
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module_exit(pmic_i2c_exit);
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MODULE_DESCRIPTION("Crystal Cove support for ValleyView2 PMIC");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Yang Bin <bin.yang@intel.com");
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