398 lines
11 KiB
C
398 lines
11 KiB
C
/*
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* pmic_ccsm.h - Intel MID PMIC CCSM Driver header file
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*
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* Copyright (C) 2011 Intel Corporation
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* Author: Jenny TC <jenny.tc@intel.com>
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*/
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#ifndef __PMIC_CCSM_H__
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#define __PMIC_CCSM_H__
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#include <asm/pmic_pdata.h>
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/*********************************************************************
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* Generic defines
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*********************************************************************/
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#define D7 (1 << 7)
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#define D6 (1 << 6)
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#define D5 (1 << 5)
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#define D4 (1 << 4)
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#define D3 (1 << 3)
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#define D2 (1 << 2)
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#define D1 (1 << 1)
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#define D0 (1 << 0)
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#define PMIC_ID_ADDR 0x00
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#define PMIC_VENDOR_ID_MASK (0x03 << 6)
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#define PMIC_MINOR_REV_MASK 0x07
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#define PMIC_MAJOR_REV_MASK (0x07 << 3)
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#define BASINCOVE_VENDORID (0x03 << 6)
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#define SHADYCOVE_VENDORID 0x00
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#define BC_PMIC_MAJOR_REV_A0 0x00
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#define BC_PMIC_MAJOR_REV_B0 (0x01 << 3)
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#define PMIC_BZONE_LOW 0
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#define PMIC_BZONE_HIGH 5
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#define PMIC_BZONE_UNKNOWN 7
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#define IRQLVL1_ADDR 0x01
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#define IRQLVL1_MASK_ADDR 0x0c
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#define IRQLVL1_CHRGR_MASK D5
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#define THRMZN0H_ADDR_BC 0xCE
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#define THRMZN0L_ADDR_BC 0xCF
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#define THRMZN1H_ADDR_BC 0xD0
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#define THRMZN1L_ADDR_BC 0xD1
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#define THRMZN2H_ADDR_BC 0xD2
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#define THRMZN2L_ADDR_BC 0xD3
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#define THRMZN3H_ADDR_BC 0xD4
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#define THRMZN3L_ADDR_BC 0xD5
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#define THRMZN4H_ADDR_BC 0xD6
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#define THRMZN4L_ADDR_BC 0xD7
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#define THRMZN0H_ADDR_SC 0xD7
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#define THRMZN0L_ADDR_SC 0xD8
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#define THRMZN1H_ADDR_SC 0xD9
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#define THRMZN1L_ADDR_SC 0xDA
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#define THRMZN2H_ADDR_SC 0xDD
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#define THRMZN2L_ADDR_SC 0xDE
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#define THRMZN3H_ADDR_SC 0xDF
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#define THRMZN3L_ADDR_SC 0xE0
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#define THRMZN4H_ADDR_SC 0xE1
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#define THRMZN4L_ADDR_SC 0xE2
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#define CHGRIRQ0_ADDR 0x07
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#define CHGIRQ0_BZIRQ_MASK D7
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#define CHGIRQ0_BAT_CRIT_MASK D6
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#define CHGIRQ0_BAT1_ALRT_MASK D5
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#define CHGIRQ0_BAT0_ALRT_MASK D4
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#define MCHGRIRQ0_ADDR 0x12
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#define MCHGIRQ0_RSVD_MASK D7
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#define MCHGIRQ0_MBAT_CRIT_MASK D6
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#define MCHGIRQ0_MBAT1_ALRT_MASK D5
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#define MCHGIRQ0_MBAT0_ALRT_MASK D4
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#define SCHGRIRQ0_ADDR 0x4E
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#define SCHGIRQ0_RSVD_MASK D7
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#define SCHGIRQ0_SBAT_CRIT_MASK D6
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#define SCHGIRQ0_SBAT1_ALRT_MASK D5
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#define SCHGIRQ0_SBAT0_ALRT_MASK D4
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#define LOWBATTDET0_ADDR 0x2C
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#define LOWBATTDET1_ADDR 0x2D
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#define BATTDETCTRL_ADDR 0x2E
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#define VBUSDETCTRL_ADDR 0x50
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#define VDCINDETCTRL_ADDR 0x51
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#define CHRGRIRQ1_ADDR 0x08
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#define CHRGRIRQ1_SUSBIDGNDDET_MASK D4
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#define CHRGRIRQ1_SUSBIDFLTDET_MASK D3
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#define CHRGRIRQ1_SUSBIDDET_MASK D3
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#define CHRGRIRQ1_SBATTDET_MASK D2
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#define CHRGRIRQ1_SDCDET_MASK D1
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#define CHRGRIRQ1_SVBUSDET_MASK D0
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#define MCHGRIRQ1_ADDR 0x13
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#define MCHRGRIRQ1_SUSBIDGNDDET_MASK D4
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#define MCHRGRIRQ1_SUSBIDFLTDET_MASK D3
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#define MCHRGRIRQ1_SUSBIDDET_MASK D3
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#define MCHRGRIRQ1_SBATTDET_MAS D2
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#define MCHRGRIRQ1_SDCDET_MASK D1
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#define MCHRGRIRQ1_SVBUSDET_MASK D0
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#define SCHGRIRQ1_ADDR 0x4F
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#define SCHRGRIRQ1_SUSBIDGNDDET_MASK (D3|D4)
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#define SCHRGRIRQ1_SUSBIDDET_MASK D3
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#define SCHRGRIRQ1_SBATTDET_MASK D2
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#define SCHRGRIRQ1_SDCDET_MASK D1
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#define SCHRGRIRQ1_SVBUSDET_MASK D0
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#define SHRT_GND_DET (0x01 << 3)
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#define SHRT_FLT_DET (0x01 << 4)
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#define PMIC_CHRGR_INT0_MASK 0xB1
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#define PMIC_CHRGR_CCSM_INT0_MASK 0xB0
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#define PMIC_CHRGR_EXT_CHRGR_INT_MASK 0x01
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#define CHGRCTRL0_ADDR 0x4B
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#define CHGRCTRL0_WDT_NOKICK_MASK D7
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#define CHGRCTRL0_DBPOFF_MASK D6
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#define CHGRCTRL0_CCSM_OFF_MASK D5
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#define CHGRCTRL0_TTLCK_MASK D4
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#define CHGRCTRL0_SWCONTROL_MASK D3
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#define CHGRCTRL0_EXTCHRDIS_MASK D2
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#define CHRCTRL0_EMRGCHREN_MASK D1
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#define CHRCTRL0_CHGRRESET_MASK D0
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#define WDT_NOKICK_ENABLE (0x01 << 7)
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#define WDT_NOKICK_DISABLE (~WDT_NOKICK_ENABLE & 0xFF)
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#define EXTCHRDIS_ENABLE (0x01 << 2)
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#define EXTCHRDIS_DISABLE (~EXTCHRDIS_ENABLE & 0xFF)
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#define SWCONTROL_ENABLE (0x01 << 3)
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#define EMRGCHREN_ENABLE (0x01 << 1)
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#define CHGRCTRL1_ADDR 0x4C
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#define CHGRCTRL1_DBPEN_MASK D7
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#define CHGRCTRL1_OTGMODE_MASK D6
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#define CHGRCTRL1_FTEMP_EVENT_MASK D5
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#define CHGRCTRL1_FUSB_INLMT_1500 D4
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#define CHGRCTRL1_FUSB_INLMT_900 D3
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#define CHGRCTRL1_FUSB_INLMT_500 D2
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#define CHGRCTRL1_FUSB_INLMT_150 D1
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#define CHGRCTRL1_FUSB_INLMT_100 D0
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#define CHGRSTATUS_ADDR 0x4D
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#define CHGRSTATUS_RSVD_MASK (D7|D6|D5|D3)
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#define CHGRSTATUS_SDPB_MASK D4
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#define CHGRSTATUS_CHGDISLVL_MASK D2
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#define CHGRSTATUS_CHGDETB_LATCH_MASK D1
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#define CHGDETB_MASK D0
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#define THRMBATZONE_ADDR_BC 0xB5
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#define THRMBATZONE_ADDR_SC 0xB6
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#define THRMBATZONE_MASK (D0|D1|D2)
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#define USBIDCTRL_ADDR 0x19
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#define USBIDEN_MASK 0x01
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#define ACADETEN_MASK (0x01 << 1)
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#define USBIDSTAT_ADDR 0x1A
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#define ID_SHORT D4
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#define ID_SHORT_VBUS (1 << 4)
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#define ID_NOT_SHORT_VBUS 0
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#define ID_FLOAT_STS D3
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#define R_ID_FLOAT_DETECT (1 << 3)
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#define R_ID_FLOAT_NOT_DETECT 0
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#define ID_RAR_BRC_STS ((D2 | D1))
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#define ID_ACA_NOT_DETECTED 0
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#define R_ID_A (1 << 1)
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#define R_ID_B (2 << 1)
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#define R_ID_C (3 << 1)
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#define ID_GND D0
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#define ID_TYPE_A 0
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#define ID_TYPE_B 1
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#define is_aca(x) ((x & R_ID_A) || (x & R_ID_B) || (x & R_ID_C))
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#define WAKESRC_ADDR 0x24
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#define CHRTTADDR_ADDR 0x56
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#define CHRTTDATA_ADDR 0x57
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#define USBSRCDET_RETRY_CNT 5
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#define USBSRCDET_SLEEP_TIME 200
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#define USBSRCDETSTATUS_ADDR 0x5D
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#define USBSRCDET_SUSBHWDET_MASK (D0|D1)
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#define USBSRCDET_USBSRCRSLT_MASK (D2|D3|D4|D5)
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#define USBSRCDET_SDCD_MASK (D6|D7)
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#define USBSRCDET_SUSBHWDET_DETON (0x01 << 0)
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#define USBSRCDET_SUSBHWDET_DETSUCC (0x01 << 1)
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#define USBSRCDET_SUSBHWDET_DETFAIL (0x03 << 0)
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#define USBPHYCTRL_ADDR 0x30
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#define USBPHYCTRL_CHGDET_N_POL_MASK D1
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#define USBPHYCTRL_USBPHYRSTB_MASK D0
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/* Registers on I2C-dev2-0x6E */
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#define USBPATH_ADDR 0x011C
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#define USBPATH_USBSEL_MASK D3
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#define HVDCPDET_SLEEP_TIME 2000
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#define DBG_USBBC1_ADDR 0x01B7
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#define DBG_USBBC1_SWCTRL_EN_MASK D7
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#define DBG_USBBC1_EN_CMP_DM_MASK D2
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#define DBG_USBBC1_EN_CMP_DP_MASK D1
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#define DBG_USBBC1_EN_CHG_DET_MASK D0
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#define DBG_USBBC2_ADDR 0x01B8
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#define DBG_USBBC2_EN_VDMSRC_MASK D1
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#define DBG_USBBC2_EN_VDPSRC_MASK D0
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#define DBG_USBBCSTAT_ADDR 0x01B9
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#define DBG_USBBCSTAT_VDATDET_MASK D2
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#define DBG_USBBCSTAT_CMP_DM_MASK D1
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#define DBG_USBBCSTAT_CMP_DP_MASK D0
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#define TT_I2CDADDR_ADDR 0x00
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#define TT_CHGRINIT0OS_ADDR 0x01
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#define TT_CHGRINIT1OS_ADDR 0x02
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#define TT_CHGRINIT2OS_ADDR 0x03
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#define TT_CHGRINIT3OS_ADDR 0x04
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#define TT_CHGRINIT4OS_ADDR 0x05
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#define TT_CHGRINIT5OS_ADDR 0x06
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#define TT_CHGRINIT6OS_ADDR 0x07
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#define TT_CHGRINIT7OS_ADDR 0x08
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#define TT_USBINPUTICCOS_ADDR 0x09
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#define TT_USBINPUTICCMASK_ADDR 0x0A
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#define TT_CHRCVOS_ADDR 0X0B
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#define TT_CHRCVMASK_ADDR 0X0C
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#define TT_CHRCCOS_ADDR 0X0D
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#define TT_CHRCCMASK_ADDR 0X0E
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#define TT_LOWCHROS_ADDR 0X0F
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#define TT_LOWCHRMASK_ADDR 0X10
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#define TT_WDOGRSTOS_ADDR 0X11
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#define TT_WDOGRSTMASK_ADDR 0X12
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#define TT_CHGRENOS_ADDR 0X13
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#define TT_CHGRENMASK_ADDR 0X14
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#define TT_CUSTOMFIELDEN_ADDR 0X15
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#define TT_HOT_LC_EN D1
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#define TT_COLD_LC_EN D0
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#define TT_HOT_COLD_LC_MASK (TT_HOT_LC_EN | TT_COLD_LC_EN)
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#define TT_HOT_COLD_LC_EN (TT_HOT_LC_EN | TT_COLD_LC_EN)
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#define TT_HOT_COLD_LC_DIS 0
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#define TT_CHGRINIT0VAL_ADDR 0X20
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#define TT_CHGRINIT1VAL_ADDR 0X21
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#define TT_CHGRINIT2VAL_ADDR 0X22
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#define TT_CHGRINIT3VAL_ADDR 0X23
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#define TT_CHGRINIT4VAL_ADDR 0X24
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#define TT_CHGRINIT5VAL_ADDR 0X25
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#define TT_CHGRINIT6VAL_ADDR 0X26
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#define TT_CHGRINIT7VAL_ADDR 0X27
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#define TT_USBINPUTICC100VAL_ADDR 0X28
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#define TT_USBINPUTICC150VAL_ADDR 0X29
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#define TT_USBINPUTICC500VAL_ADDR 0X2A
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#define TT_USBINPUTICC900VAL_ADDR 0X2B
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#define TT_USBINPUTICC1500VAL_ADDR 0X2C
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#define TT_CHRCVEMRGLOWVAL_ADDR 0X2D
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#define TT_CHRCVCOLDVAL_ADDR 0X2E
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#define TT_CHRCVCOOLVAL_ADDR 0X2F
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#define TT_CHRCVWARMVAL_ADDR 0X30
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#define TT_CHRCVHOTVAL_ADDR 0X31
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#define TT_CHRCVEMRGHIVAL_ADDR 0X32
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#define TT_CHRCCEMRGLOWVAL_ADDR 0X33
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#define TT_CHRCCCOLDVAL_ADDR 0X34
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#define TT_CHRCCCOOLVAL_ADDR 0X35
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#define TT_CHRCCWARMVAL_ADDR 0X36
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#define TT_CHRCCHOTVAL_ADDR 0X37
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#define TT_CHRCCEMRGHIVAL_ADDR 0X38
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#define TT_LOWCHRENVAL_ADDR 0X39
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#define TT_LOWCHRDISVAL_ADDR 0X3A
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#define TT_WDOGRSTVAL_ADDR 0X3B
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#define TT_CHGRENVAL_ADDR 0X3C
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#define TT_CHGRDISVAL_ADDR 0X3D
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/*Interrupt registers*/
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#define BATT_CHR_BATTDET_MASK D2
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/*Status registers*/
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#define BATT_PRESENT 1
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#define BATT_NOT_PRESENT 0
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#define BATT_STRING_MAX 8
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#define BATTID_STR_LEN 8
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#define CHARGER_PRESENT 1
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#define CHARGER_NOT_PRESENT 0
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/*FIXME: Modify default values */
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#define BATT_DEAD_CUTOFF_VOLT 3400 /* 3400 mV */
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#define BATT_CRIT_CUTOFF_VOLT 3700 /* 3700 mV */
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#define MSIC_BATT_TEMP_MAX 60 /* 60 degrees */
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#define MSIC_BATT_TEMP_MIN 0
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#define BATT_TEMP_WARM 45 /* 45 degrees */
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#define MIN_BATT_PROF 4
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#define PMIC_REG_NAME_LEN 28
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#define PMIC_REG_DEF(x) { .reg_name = #x, .addr = x }
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struct interrupt_info {
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/* Interrupt register mask*/
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u8 int_reg_mask;
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/* interrupt status register mask */
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u8 stat_reg_mask;
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/* log message if interrupt is set */
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char *log_msg_int_reg_true;
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/* log message if stat is true or false */
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char *log_msg_stat_true;
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char *log_msg_stat_false;
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/* handle if interrupt bit is set */
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void (*int_handle) (void);
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/* interrupt status handler */
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void (*stat_handle) (bool);
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};
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enum pmic_charger_aca_type {
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RID_UNKNOWN = 0,
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RID_A,
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RID_B,
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RID_C,
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RID_FLOAT,
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RID_GND,
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};
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enum pmic_charger_cable_type {
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PMIC_CHARGER_TYPE_NONE = 0,
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PMIC_CHARGER_TYPE_SDP,
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PMIC_CHARGER_TYPE_DCP,
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PMIC_CHARGER_TYPE_CDP,
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PMIC_CHARGER_TYPE_ACA,
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PMIC_CHARGER_TYPE_SE1,
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PMIC_CHARGER_TYPE_MHL,
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PMIC_CHARGER_TYPE_FLOAT_DP_DN,
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PMIC_CHARGER_TYPE_OTHER,
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PMIC_CHARGER_TYPE_DCP_EXTPHY,
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};
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struct pmic_chrgr_drv_context {
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bool invalid_batt;
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bool is_batt_present;
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bool current_sense_enabled;
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unsigned int irq; /* GPE_ID or IRQ# */
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void __iomem *pmic_intr_iomap;
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struct device *dev;
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int health;
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u8 pmic_id;
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bool is_internal_usb_phy;
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enum pmic_charger_cable_type charger_type;
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/* ShadyCove-WA for VBUS removal detect issue */
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bool vbus_connect_status;
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bool otg_mode_enabled;
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struct ps_batt_chg_prof *sfi_bcprof;
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struct ps_pse_mod_prof *actual_bcprof;
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struct ps_pse_mod_prof *runtime_bcprof;
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struct pmic_platform_data *pdata;
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struct usb_phy *otg;
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struct list_head evt_queue;
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struct work_struct evt_work;
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struct mutex evt_queue_lock;
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struct wake_lock wakelock;
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struct wake_lock otg_wa_wakelock;
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};
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struct pmic_event {
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struct list_head node;
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u8 chgrirq0_int;
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u8 chgrirq1_int;
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u8 chgrirq0_stat;
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u8 chgrirq1_stat;
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};
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struct pmic_regs_def {
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char reg_name[PMIC_REG_NAME_LEN];
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u16 addr;
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};
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#endif
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