280 lines
6.9 KiB
C
280 lines
6.9 KiB
C
/**************************************************************************
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* Copyright (c) 2007-2008, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#ifndef _VXD_DRM_H_
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#define _VXD_DRM_H_
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
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#include "drm.h"
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#else
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#include <uapi/drm/drm.h>
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#endif
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#if defined(__linux__) && !defined(__KERNEL__)
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#include<stdint.h>
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#include <linux/types.h>
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#include "drm_mode.h"
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#endif
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#include "psb_ttm_fence_user.h"
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#include "psb_ttm_placement_user.h"
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#define DRM_PSB_EXTENSION 0x50
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#define DRM_PSB_GETPAGEADDRS 0x51
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#define DRM_PSB_CMDBUF 0x52
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#define DRM_PSB_TTM_PL_CREATE 0x53
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#define DRM_PSB_TTM_PL_REFERENCE 0x54
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#define DRM_PSB_TTM_PL_UNREF 0x55
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#define DRM_PSB_TTM_PL_SYNCCPU 0x56
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#define DRM_PSB_TTM_PL_WAITIDLE 0x57
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#define DRM_PSB_TTM_PL_SETSTATUS 0x58
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#define DRM_PSB_TTM_PL_CREATE_UB 0x59
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#define DRM_PSB_TTM_FENCE_SIGNALED 0x5a
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#define DRM_PSB_TTM_FENCE_FINISH 0x5b
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#define DRM_PSB_TTM_FENCE_UNREF 0x5c
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#define DRM_PSB_VIDEO_GETPARAM 0x5d
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#define DRM_COMMAND_VXD_OFFSET 0x50
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#define DRM_COMMAND_VXD_BASE 0x90
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#define DRM_PSB_PLACEMENT_OFFSET 0x53
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#define DRM_PSB_FENCE_OFFSET 0x5a
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#define PSB_RELOC_MAGIC 0x67676767
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#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
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#define PSB_RELOC_SHIFT_SHIFT 0
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#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
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#define PSB_RELOC_ALSHIFT_SHIFT 16
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#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
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* buffer
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*/
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struct drm_psb_reloc {
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uint32_t reloc_op;
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uint32_t where; /* offset in destination buffer */
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uint32_t buffer; /* Buffer reloc applies to */
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uint32_t mask; /* Destination format: */
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uint32_t shift; /* Destination format: */
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uint32_t pre_add; /* Destination format: */
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uint32_t background; /* Destination add */
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uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
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uint32_t arg0; /* Reloc-op dependant */
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uint32_t arg1;
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};
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#define PSB_GPU_ACCESS_READ (1ULL << 32)
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#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
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#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
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#define PSB_BO_FLAG_COMMAND (1ULL << 52)
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#define PSB_ENGINE_2D 2
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#define PSB_ENGINE_DECODE 0
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#define PSB_ENGINE_VIDEO 0
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#define LNC_ENGINE_ENCODE 1
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#define VSP_ENGINE_VPP 6
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/*
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* For this fence class we have a couple of
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* fence types.
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*/
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#define _PSB_FENCE_EXE_SHIFT 0
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#define _PSB_FENCE_FEEDBACK_SHIFT 4
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#define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT)
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#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
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#define PSB_NUM_ENGINES 7
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#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
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struct drm_psb_extension_rep {
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int32_t exists;
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uint32_t driver_ioctl_offset;
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uint32_t sarea_offset;
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uint32_t major;
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uint32_t minor;
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uint32_t pl;
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};
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#define DRM_PSB_EXT_NAME_LEN 128
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union drm_psb_extension_arg {
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char extension[DRM_PSB_EXT_NAME_LEN];
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struct __user drm_psb_extension_rep rep;
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};
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struct psb_validate_req {
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uint64_t set_flags;
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uint64_t clear_flags;
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uint64_t next;
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uint64_t presumed_gpu_offset;
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uint32_t buffer_handle;
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uint32_t presumed_flags;
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uint32_t group;
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uint32_t pad64;
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};
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struct psb_validate_rep {
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uint64_t gpu_offset;
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uint32_t placement;
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uint32_t fence_type_mask;
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};
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#define PSB_USE_PRESUMED (1 << 0)
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struct psb_validate_arg {
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uint64_t handled;
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uint64_t ret;
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union {
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struct psb_validate_req req;
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struct psb_validate_rep rep;
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} d;
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};
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#define DRM_PSB_FENCE_NO_USER (1 << 0)
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struct psb_ttm_fence_rep {
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uint32_t handle;
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uint32_t fence_class;
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uint32_t fence_type;
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uint32_t signaled_types;
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uint32_t error;
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};
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typedef struct drm_psb_cmdbuf_arg {
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uint64_t buffer_list; /* List of buffers to validate */
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uint64_t fence_arg;
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uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
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uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
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uint32_t cmdbuf_size;
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uint32_t reloc_handle; /* Reloc buffer object */
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uint32_t reloc_offset;
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uint32_t num_relocs;
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/* Not implemented yet */
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uint32_t fence_flags;
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uint32_t engine;
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} drm_psb_cmdbuf_arg_t;
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struct drm_psb_pageflip_arg_t {
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uint32_t flip_offset;
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uint32_t stride;
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};
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enum lnc_getparam_key {
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LNC_VIDEO_DEVICE_INFO,
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LNC_VIDEO_GETPARAM_RAR_INFO,
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LNC_VIDEO_GETPARAM_CI_INFO,
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LNC_VIDEO_FRAME_SKIP,
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IMG_VIDEO_DECODE_STATUS,
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IMG_VIDEO_NEW_CONTEXT,
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IMG_VIDEO_RM_CONTEXT,
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IMG_VIDEO_UPDATE_CONTEXT,
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IMG_VIDEO_MB_ERROR,
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IMG_VIDEO_SET_DISPLAYING_FRAME,
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IMG_VIDEO_GET_DISPLAYING_FRAME,
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IMG_VIDEO_GET_HDMI_STATE,
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IMG_VIDEO_SET_HDMI_STATE,
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PNW_VIDEO_QUERY_ENTRY,
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IMG_DISPLAY_SET_WIDI_EXT_STATE,
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IMG_VIDEO_IED_STATE
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};
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struct drm_lnc_video_getparam_arg {
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uint64_t key;
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uint64_t arg; /* argument pointer */
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uint64_t value; /* feed back pointer */
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};
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struct drm_video_displaying_frameinfo {
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uint32_t buf_handle;
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uint32_t width;
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uint32_t height;
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uint32_t size; /* buffer size */
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uint32_t format; /* fourcc */
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uint32_t luma_stride; /* luma stride */
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uint32_t chroma_u_stride; /* chroma stride */
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uint32_t chroma_v_stride;
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uint32_t luma_offset; /* luma offset from the beginning of the memory */
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uint32_t chroma_u_offset; /* UV offset from the beginning of the memory */
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uint32_t chroma_v_offset;
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uint32_t reserved;
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};
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struct drm_psb_dev_info_arg {
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uint32_t num_use_attribute_registers;
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};
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#define DRM_PSB_DEVINFO 0x01
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struct drm_psb_sizes_arg {
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uint32_t ta_mem_size;
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uint32_t mmu_size;
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uint32_t pds_size;
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uint32_t rastgeom_size;
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uint32_t tt_size;
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uint32_t vram_size;
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};
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/*
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* Public memory types.
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*/
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#define DRM_PSB_MEM_MMU TTM_PL_PRIV1
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#define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1
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#define TTM_PL_CI TTM_PL_PRIV0
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#define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0
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#define TTM_PL_RAR TTM_PL_PRIV2
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#define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2
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#define DRM_PSB_MEM_MMU_TILING TTM_PL_PRIV3
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#define DRM_PSB_FLAG_MEM_MMU_TILING TTM_PL_FLAG_PRIV3
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#define MAX_SLICES_PER_PICTURE 72
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struct psb_msvdx_mb_region {
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uint32_t start;
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uint32_t end;
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};
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typedef struct drm_psb_msvdx_decode_status {
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uint32_t num_region;
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struct psb_msvdx_mb_region mb_regions[MAX_SLICES_PER_PICTURE];
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} drm_psb_msvdx_decode_status_t;
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/*Status of the command sent to the gfx device.*/
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enum drm_cmd_status {
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DRM_CMD_SUCCESS,
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DRM_CMD_FAILED,
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DRM_CMD_HANG
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};
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struct drm_psb_getpageaddrs_arg {
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uint64_t handle;
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uint64_t page_addrs;
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uint64_t gtt_offset;
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};
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#endif /* _IVXD_DRM_H_ */
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