317 lines
8.4 KiB
C
317 lines
8.4 KiB
C
/**************************************************************************
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*
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* Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA
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* Copyright (c) Imagination Technologies Limited, UK
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#ifndef _FPGA_TOPAZ_H_
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#define _FPGA_TOPAZ_H_
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#include "psb_drv.h"
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#include "tng_topaz_hw_reg.h"
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#define TOPAZ_MTX_REG_SIZE (34 * 4 + 183 * 4)
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/*Must be equal to IMG_CODEC_NUM*/
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#define TNG_TOPAZ_CODEC_NUM_MAX (25)
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#define TNG_TOPAZ_BIAS_TABLE_MAX_SIZE (2 * 1024)
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/*#define TOPAZ_PDUMP*/
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#define TOPAZHP_IRQ_ENABLED
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#define TOPAZHP_PIPE_NUM 2
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/* #define MRFLD_B0_DEBUG */
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#define TNG_IS_H264_ENC(codec) \
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(codec == IMG_CODEC_H264_NO_RC || \
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codec == IMG_CODEC_H264_VBR || \
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codec == IMG_CODEC_H264_VCM || \
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codec == IMG_CODEC_H264_CBR || \
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codec == IMG_CODEC_H264_LLRC || \
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codec == IMG_CODEC_H264_ALL_RC)
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#define TNG_IS_H264MVC_ENC(codec) \
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(codec == IMG_CODEC_H264MVC_NO_RC || \
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codec == IMG_CODEC_H264MVC_CBR || \
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codec == IMG_CODEC_H264MVC_VBR)
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#define TNG_IS_JPEG_ENC(codec) \
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(codec == IMG_CODEC_JPEG)
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#define MASK_WB_HIGH_CMDID 0xFF000000
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#define SHIFT_WB_HIGH_CMDID 24
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#define MASK_WB_LOW_CMDID 0x00FFFF00
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#define SHIFT_WB_LOW_CMDID 8
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#define MASK_WB_SYNC_CNT 0x000000FF
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#define SHIFT_WB_SYNC_CNT 0
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#define MAX_CMD_SIZE 4096
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#define SHIFT_MTX_MSG_PRIORITY (7)
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#define MASK_MTX_MSG_PRIORITY (0x1 << SHIFT_MTX_MSG_PRIORITY)
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#define SHIFT_MTX_MSG_CORE (8)
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#define MASK_MTX_MSG_CORE (0x7f << SHIFT_MTX_MSG_CORE)
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#define SHIFT_MTX_MSG_WB_INTERRUPT (15)
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#define MASK_MTX_MSG_WB_INTERRUPT (0x1 << SHIFT_MTX_MSG_WB_INTERRUPT)
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#define SHIFT_MTX_MSG_COUNT (16)
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#define MASK_MTX_MSG_COUNT (0xffff << SHIFT_MTX_MSG_COUNT)
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/*#define VERIFYFW*/
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/*#define VERIFY_CONTEXT_SWITCH*/
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enum TOPAZ_REG_ID {
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TOPAZ_MULTICORE_REG,
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TOPAZ_CORE_REG,
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TOPAZ_VLC_REG
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};
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extern int drm_topaz_pmpolicy;
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extern int drm_topaz_cgpolicy;
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extern int drm_topaz_cmdpolicy;
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extern int drm_topaz_pmlatency;
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/* XXX: it's a copy of msvdx cmd queue. should have some change? */
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struct tng_topaz_cmd_queue {
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struct drm_file *file_priv;
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struct list_head head;
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void *cmd;
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uint32_t cmd_size;
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uint32_t sequence;
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};
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#define SECURE_VRL_HEADER 728
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#define SECURE_FIP_HEADER 296
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struct tng_secure_fw {
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uint32_t codec_idx;
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uint32_t addr_data;
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uint32_t text_size;
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uint32_t data_size;
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uint32_t data_loca;
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struct ttm_buffer_object *text;
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struct ttm_buffer_object *data;
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};
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#define MAX_CONTEXT_CNT 2
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#define MAX_TOPAZHP_CORES 4
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#define MASK_TOPAZ_CONTEXT_SAVED (0x1)
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#define MASK_TOPAZ_FIRMWARE_EXIT (0x1 << 1)
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#define MASK_TOPAZ_FIRMWARE_ACTIVE (0x1 << 2)
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struct tng_topaz_private {
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unsigned int pmstate;
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struct sysfs_dirent *sysfs_pmstate;
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int frame_skip;
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#ifdef VERIFYFW
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/* For verify firmware */
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struct ttm_buffer_object *text_mem;
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struct ttm_buffer_object *data_mem;
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uint32_t bo_text_items[10];
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uint32_t bo_data_items[10];
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uint32_t dma_text_items[10];
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uint32_t dma_data_items[10];
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#endif
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uint32_t cur_codec;
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int topaz_needs_reset;
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void *topaz_mtx_reg_state[MAX_TOPAZHP_CORES];
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void *topaz_bias_table[MAX_TOPAZHP_CORES];
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uint32_t cur_mtx_data_size[MAX_TOPAZHP_CORES];
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struct ttm_buffer_object *topaz_mtx_data_mem[MAX_TOPAZHP_CORES];
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/*
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*topaz command queue
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*/
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struct tng_topaz_cmd_queue *saved_queue;
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char *saved_cmd;
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spinlock_t topaz_lock;
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struct mutex topaz_mutex;
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struct mutex ctx_mutex;
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struct list_head topaz_queue;
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atomic_t cmd_wq_free;
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atomic_t vec_ref_count;
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wait_queue_head_t cmd_wq;
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int topaz_busy; /* 0 means topaz is free */
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int topaz_fw_loaded;
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uint32_t stored_initial_qp;
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uint32_t topaz_dash_access_ctrl;
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struct ttm_buffer_object *topaz_bo; /* 4K->2K/2K for writeback/sync */
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struct ttm_bo_kmap_obj topaz_bo_kmap;
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uint32_t *topaz_mtx_wb;
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uint32_t topaz_wb_offset;
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uint32_t *topaz_sync_addr;
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uint32_t topaz_sync_offset;
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uint32_t topaz_cmd_count;
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uint32_t core_id;
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uint32_t topaz_wb_received;
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uint32_t topaz_mtx_saved;
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/* firmware */
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struct tng_secure_fw topaz_fw[TNG_TOPAZ_CODEC_NUM_MAX];
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uint32_t topaz_hw_busy;
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uint32_t topaz_num_pipes;
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/* For IRQ and Sync */
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uint32_t producer;
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uint32_t consumer;
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/* JPEG ISSUEBUF cmd count */
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uint32_t issuebuf_cmd_count;
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/* Context parameters */
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struct psb_video_ctx *cur_context;
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struct psb_video_ctx *irq_context;
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/* topaz suspend work queue */
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struct drm_device *dev;
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struct delayed_work topaz_suspend_work;
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uint32_t isr_enabled;
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uint32_t power_down_by_release;
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struct ttm_object_file *tfile;
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uint8_t vec_err;
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};
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struct tng_topaz_cmd_header {
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union {
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struct {
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uint32_t id:8;
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uint32_t core:8;
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uint32_t low_cmd_count:8;
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uint32_t high_cmd_count:8;
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};
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uint32_t val;
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};
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};
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/* external function declare */
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/*ISR of TopazSC*/
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extern bool tng_topaz_interrupt(void *pvData);
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/*topaz commad handling function*/
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extern int tng_cmdbuf_video(struct drm_file *priv,
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struct list_head *validate_list,
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uint32_t fence_type,
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struct drm_psb_cmdbuf_arg *arg,
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struct ttm_buffer_object *cmd_buffer,
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struct psb_ttm_fence_rep *fence_arg);
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extern int tng_check_topaz_idle(struct drm_device *dev);
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extern void tng_topaz_enableirq(struct drm_device *dev);
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extern void tng_topaz_disableirq(struct drm_device *dev);
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extern int tng_topaz_init(struct drm_device *dev);
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extern int tng_topaz_uninit(struct drm_device *dev);
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extern void tng_topaz_handle_timeout(struct ttm_fence_device *fdev);
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extern int32_t mtx_write_core_reg(struct drm_psb_private *dev_priv,
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uint32_t reg,
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const uint32_t val);
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extern int32_t mtx_read_core_reg(struct drm_psb_private *dev_priv,
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uint32_t reg,
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uint32_t *ret_val);
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int tng_topaz_kick_null_cmd(struct drm_device *dev,
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uint32_t sync_seq);
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void tng_set_producer(struct drm_device *dev,
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uint32_t consumer);
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void tng_set_consumer(struct drm_device *dev,
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uint32_t consumer);
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uint32_t tng_get_producer(struct drm_device *dev);
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uint32_t tng_get_consumer(struct drm_device *dev);
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uint32_t tng_serialize(struct drm_device *dev);
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uint32_t tng_wait_for_ctrl(struct drm_device *dev,
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uint32_t control);
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int mtx_upload_fw(struct drm_device *dev,
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uint32_t codec,
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struct psb_video_ctx *video_ctx);
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int32_t mtx_dma_read(struct drm_device *dev,
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struct ttm_buffer_object *dst_bo,
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uint32_t src_ram_addr,
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uint32_t size);
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void mtx_start(struct drm_device *dev);
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void mtx_stop(struct drm_psb_private *dev_priv);
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void mtx_kick(struct drm_device *dev);
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int mtx_write_FIFO(struct drm_device *dev,
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struct tng_topaz_cmd_header *cmd_header,
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uint32_t param, uint32_t param_addr, uint32_t sync_seq);
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int tng_topaz_remove_ctx(struct drm_psb_private *dev,
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struct psb_video_ctx *video_ctx);
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void tng_topaz_mmu_hwsetup(struct drm_psb_private *dev_priv,
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struct psb_video_ctx *video_ctx);
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extern int tng_topaz_save_mtx_state(struct drm_device *dev);
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extern int tng_topaz_restore_mtx_state(struct drm_device *dev);
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extern int tng_topaz_restore_mtx_state_b0(struct drm_device *dev);
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int tng_topaz_dequeue_send(struct drm_device *dev);
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uint32_t get_ctx_cnt(struct drm_device *dev);
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struct psb_video_ctx *get_ctx_from_fp(
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struct drm_device *dev, struct file *filp);
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void tng_topaz_handle_sigint(
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struct drm_device *dev,
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struct file *filp);
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void tng_topaz_CG_disable(struct drm_device *dev);
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int tng_topaz_set_vec_freq(u32 freq_code);
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bool power_island_get_dummy(struct drm_device *dev);
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bool power_island_put_dummy(struct drm_device *dev);
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#define TNG_TOPAZ_NEW_PMSTATE(drm_dev, topaz_priv, new_state) \
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do { \
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topaz_priv->pmstate = new_state; \
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sysfs_notify_dirent(topaz_priv->sysfs_pmstate); \
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PSB_DEBUG_PM("TOPAZ: %s\n", \
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(new_state == PSB_PMSTATE_POWERUP) ? "powerup" : "powerdown"); \
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} while (0)
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#endif /* _FPGA_TOPAZ_H_ */
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