271 lines
8.7 KiB
C
271 lines
8.7 KiB
C
/*
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* Misc utility routines for accessing PMU corerev specific features
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* of the SiliconBackplane-based Broadcom chips.
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*
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* Copyright (C) 1999-2013, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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* $Id: hndpmu.c 385540 2013-02-15 23:14:50Z $
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*/
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/*
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* Note: this file contains PLL/FLL related functions. A chip can contain multiple PLLs/FLLs.
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* However, in the context of this file the baseband ('BB') PLL/FLL is referred to.
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*
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* Throughout this code, the prefixes 'pmu0_', 'pmu1_' and 'pmu2_' are used.
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* They refer to different revisions of the PMU (which is at revision 18 @ Apr 25, 2012)
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* pmu2_ marks the transition from PLL to ADFLL (Digital Frequency Locked Loop)
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*/
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#include <bcm_cfg.h>
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#include <typedefs.h>
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#include <bcmdefs.h>
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#include <osl.h>
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#include <bcmutils.h>
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#include <siutils.h>
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#include <bcmdevs.h>
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#include <hndsoc.h>
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#include <sbchipc.h>
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#include <hndpmu.h>
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#define PMU_ERROR(args)
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#define PMU_MSG(args)
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/* To check in verbose debugging messages not intended
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* to be on except on private builds.
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*/
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#define PMU_NONE(args)
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/* SDIO Pad drive strength to select value mappings.
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* The last strength value in each table must be 0 (the tri-state value).
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*/
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typedef struct {
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uint8 strength; /* Pad Drive Strength in mA */
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uint8 sel; /* Chip-specific select value */
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} sdiod_drive_str_t;
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/* SDIO Drive Strength to sel value table for PMU Rev 1 */
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static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = {
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{4, 0x2},
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{2, 0x3},
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{1, 0x0},
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{0, 0x0} };
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/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
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static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = {
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{12, 0x7},
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{10, 0x6},
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{8, 0x5},
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{6, 0x4},
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{4, 0x2},
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{2, 0x1},
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{0, 0x0} };
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/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
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static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = {
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{32, 0x7},
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{26, 0x6},
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{22, 0x5},
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{16, 0x4},
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{12, 0x3},
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{8, 0x2},
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{4, 0x1},
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{0, 0x0} };
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/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8v) */
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static const sdiod_drive_str_t sdiod_drive_strength_tab4_1v8[] = {
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{32, 0x6},
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{26, 0x7},
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{22, 0x4},
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{16, 0x5},
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{12, 0x2},
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{8, 0x3},
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{4, 0x0},
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{0, 0x1} };
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/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.2v) */
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/* SDIO Drive Strength to sel value table for PMU Rev 11 (2.5v) */
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/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
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static const sdiod_drive_str_t sdiod_drive_strength_tab5_1v8[] = {
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{6, 0x7},
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{5, 0x6},
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{4, 0x5},
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{3, 0x4},
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{2, 0x2},
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{1, 0x1},
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{0, 0x0} };
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/* SDIO Drive Strength to sel value table for PMU Rev 13 (3.3v) */
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/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
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static const sdiod_drive_str_t sdiod_drive_strength_tab6_1v8[] = {
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{3, 0x3},
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{2, 0x2},
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{1, 0x1},
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{0, 0x0} };
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/*
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* SDIO Drive Strength to sel value table for 43143 PMU Rev 17, see Confluence 43143 Toplevel
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* architecture page, section 'PMU Chip Control 1 Register definition', click link to picture
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* BCM43143_sel_sdio_signals.jpg. Valid after PMU Chip Control 0 Register, bit31 (override) has
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* been written '1'.
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*/
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#if !defined(BCM_SDIO_VDDIO) || BCM_SDIO_VDDIO == 33
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static const sdiod_drive_str_t sdiod_drive_strength_tab7_3v3[] = {
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/* note: for 14, 10, 6 and 2mA hw timing is not met according to rtl team */
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{16, 0x7},
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{12, 0x5},
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{8, 0x3},
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{4, 0x1} }; /* note: 43143 does not support tristate */
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#else
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static const sdiod_drive_str_t sdiod_drive_strength_tab7_1v8[] = {
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/* note: for 7, 5, 3 and 1mA hw timing is not met according to rtl team */
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{8, 0x7},
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{6, 0x5},
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{4, 0x3},
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{2, 0x1} }; /* note: 43143 does not support tristate */
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#endif /* BCM_SDIO_VDDIO */
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#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
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/**
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* Balance between stable SDIO operation and power consumption is achieved using this function.
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* Note that each drive strength table is for a specific VDDIO of the SDIO pads, ideally this
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* function should read the VDDIO itself to select the correct table. For now it has been solved
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* with the 'BCM_SDIO_VDDIO' preprocessor constant.
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*
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* 'drivestrength': desired pad drive strength in mA. Drive strength of 0 requests tri-state (if
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* hardware supports this), if no hw support drive strength is not programmed.
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*/
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void
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si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength)
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{
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chipcregs_t *cc;
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uint origidx, intr_val = 0;
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sdiod_drive_str_t *str_tab = NULL;
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uint32 str_mask = 0; /* only alter desired bits in PMU chipcontrol 1 register */
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uint32 str_shift = 0;
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uint32 str_ovr_pmuctl = PMU_CHIPCTL0; /* PMU chipcontrol register containing override bit */
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uint32 str_ovr_pmuval = 0; /* position of bit within this register */
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if (!(sih->cccaps & CC_CAP_PMU)) {
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return;
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}
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/* Remember original core before switch to chipc */
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cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
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switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) {
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case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
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str_mask = 0x30000000;
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str_shift = 28;
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break;
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case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
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case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
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case SDIOD_DRVSTR_KEY(BCM4315_CHIP_ID, 4):
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
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str_mask = 0x00003800;
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str_shift = 11;
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break;
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case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
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case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 11):
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if (sih->pmurev == 8) {
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab3;
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}
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else if (sih->pmurev == 11) {
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
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}
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str_mask = 0x00003800;
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str_shift = 11;
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break;
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case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12):
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
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str_mask = 0x00003800;
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str_shift = 11;
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break;
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case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab5_1v8;
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str_mask = 0x00003800;
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str_shift = 11;
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break;
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case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab6_1v8;
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str_mask = 0x00001800;
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str_shift = 11;
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break;
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case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
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#if !defined(BCM_SDIO_VDDIO) || BCM_SDIO_VDDIO == 33
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if (drivestrength >= ARRAYLAST(sdiod_drive_strength_tab7_3v3)->strength) {
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_3v3;
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}
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#else
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if (drivestrength >= ARRAYLAST(sdiod_drive_strength_tab7_1v8)->strength) {
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str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_1v8;
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}
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#endif /* BCM_SDIO_VDDIO */
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str_mask = 0x00000007;
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str_ovr_pmuval = PMU43143_CC0_SDIO_DRSTR_OVR;
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break;
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default:
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PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
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bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev));
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break;
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}
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if (str_tab != NULL && cc != NULL) {
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uint32 cc_data_temp;
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int i;
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/* Pick the lowest available drive strength equal or greater than the
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* requested strength. Drive strength of 0 requests tri-state.
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*/
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for (i = 0; drivestrength < str_tab[i].strength; i++)
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;
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if (i > 0 && drivestrength > str_tab[i].strength)
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i--;
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W_REG(osh, &cc->chipcontrol_addr, PMU_CHIPCTL1);
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cc_data_temp = R_REG(osh, &cc->chipcontrol_data);
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cc_data_temp &= ~str_mask;
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cc_data_temp |= str_tab[i].sel << str_shift;
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W_REG(osh, &cc->chipcontrol_data, cc_data_temp);
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if (str_ovr_pmuval) { /* enables the selected drive strength */
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W_REG(osh, &cc->chipcontrol_addr, str_ovr_pmuctl);
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OR_REG(osh, &cc->chipcontrol_data, str_ovr_pmuval);
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}
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PMU_MSG(("SDIO: %dmA drive strength requested; set to %dmA\n",
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drivestrength, str_tab[i].strength));
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}
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/* Return to original core */
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si_restore_core(sih, origidx, intr_val);
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} /* si_sdiod_drive_strength_init */
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