102 lines
4.5 KiB
C
102 lines
4.5 KiB
C
/*
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* pcicfg.h: PCI configuration constants and structures.
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*
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* Copyright (C) 1999-2013, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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* $Id: pcicfg.h 346935 2012-07-25 00:24:55Z $
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*/
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#ifndef _h_pcicfg_
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#define _h_pcicfg_
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/* A structure for the config registers is nice, but in most
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* systems the config space is not memory mapped, so we need
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* field offsetts. :-(
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*/
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#define PCI_CFG_VID 0
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#define PCI_CFG_DID 2
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#define PCI_CFG_CMD 4
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#define PCI_CFG_STAT 6
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#define PCI_CFG_REV 8
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#define PCI_CFG_PROGIF 9
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#define PCI_CFG_SUBCL 0xa
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#define PCI_CFG_BASECL 0xb
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#define PCI_CFG_CLSZ 0xc
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#define PCI_CFG_LATTIM 0xd
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#define PCI_CFG_HDR 0xe
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#define PCI_CFG_BIST 0xf
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#define PCI_CFG_BAR0 0x10
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#define PCI_CFG_BAR1 0x14
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#define PCI_CFG_BAR2 0x18
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#define PCI_CFG_BAR3 0x1c
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#define PCI_CFG_BAR4 0x20
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#define PCI_CFG_BAR5 0x24
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SVID 0x2c
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#define PCI_CFG_SSID 0x2e
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#define PCI_CFG_ROMBAR 0x30
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#define PCI_CFG_CAPPTR 0x34
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#define PCI_CFG_INT 0x3c
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#define PCI_CFG_PIN 0x3d
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#define PCI_CFG_MINGNT 0x3e
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#define PCI_CFG_MAXLAT 0x3f
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#define PCI_CFG_DEVCTRL 0xd8
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#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
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#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
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#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
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#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
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#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
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#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
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#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
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#define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
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#define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
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#define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
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#define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
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#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
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#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
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#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
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#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
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#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
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#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
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* 8KB window, so their address is the "regular"
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* address plus 4K
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*/
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/*
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* PCIE GEN2 changed some of the above locations for
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* Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase
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* BAR0 maps 32K of register space
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*/
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#define PCIE2_BAR0_WIN2 0x70 /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCIE2_BAR0_CORE2_WIN 0x74 /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
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/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
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#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
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#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
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#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
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#define PCI_CONFIG_SPACE_SIZE 256
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#endif /* _h_pcicfg_ */
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