1040 lines
36 KiB
C
1040 lines
36 KiB
C
/*
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* Support for Aptina AR0543_RAW camera sensor.
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*
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* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*/
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#ifndef __AR0543_RAW_H__
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#define __AR0543_RAW_H__
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#include <linux/atomisp_platform.h>
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#include <linux/atomisp.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <linux/v4l2-mediabus.h>
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#include <linux/types.h>
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#include <media/media-entity.h>
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#include <media/v4l2-chip-ident.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-subdev.h>
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//ASUS_BSP++
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#include <linux/HWVersion.h>
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extern int Read_HW_ID(void);
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//static unsigned int HW_ID = 0xFF;
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//ASUS_BSP--
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#define AR0543_RAW_RES_WIDTH_MAX 2592
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#define AR0543_RAW_RES_HEIGHT_MAX 1944
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#define MAX_FMTS 1
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#define AR0543_RAW_NAME "ar0543_raw"
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#define AR0543_RAW_ADDR 0x36
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#define AR0543_RAW_ID 0x4800
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#define AR0543_RAW_ID2 0x4b01
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#define LAST_REG_SETING {0xffff, 0xff}
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#define is_last_reg_setting(item) ((item).reg == 0xffff)
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#define I2C_MSG_LENGTH 0x2
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#define AR0543_RAW_INVALID_CONFIG 0xffffffff
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#define AR0543_RAW_MAX_FOCUS_POS 255
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#define AR0543_RAW_MAX_FOCUS_NEG (-255)
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#define AR0543_RAW_INTG_UNIT_US 100
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#define AR0543_RAW_MCLK 192
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#define AR0543_RAW_REG_BITS 16
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#define AR0543_RAW_REG_MASK 0xFFFF
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/* This should be added into include/linux/videodev2.h */
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#ifndef V4L2_IDENT_AR0543_RAW
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#define V4L2_IDENT_AR0543_RAW 8245
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#endif
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/*
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* ar0543_raw System control registers
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*/
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#define AR0543_RAW_SC_CMMN_CHIP_ID 0x0000
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#define AR0543_RAW_SC_CMMN_REV_ID 0x0002
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#define GROUPED_PARAMETER_UPDATE 0x0000
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#define GROUPED_PARAMETER_HOLD 0x0100
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#define AR0543_RAW_GROUPED_PARAMETER_HOLD 0x0104
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#define AR0543_RAW_VT_PIX_CLK_DIV 0x0300
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#define AR0543_RAW_VT_SYS_CLK_DIV 0x0302
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#define AR0543_RAW_PRE_PLL_CLK_DIV 0x0304
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#define AR0543_RAW_PLL_MULTIPLIER 0x0306
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#define AR0543_RAW_OP_PIX_DIV 0x0308
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#define AR0543_RAW_OP_SYS_DIV 0x030A
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#define AR0543_RAW_FRAME_LENGTH_LINES 0x0340
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#define AR0543_RAW_LINE_LENGTH_PCK 0x0342
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#define AR0543_RAW_COARSE_INTG_TIME_MIN 0x1004
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#define AR0543_RAW_COARSE_INTG_TIME_MAX 0x1006
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#define AR0543_RAW_FINE_INTG_TIME_MIN 0x1008
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#define AR0543_RAW_FINE_INTG_MIN_DEF 0x4FE
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#define AR0543_RAW_FINE_INTG_TIME_MAX 0x100A
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#define AR0543_RAW_FINE_INTG_MAX_DEF 0x3EE
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#define AR0543_RAW_READ_MODE 0x3040
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#define AR0543_RAW_READ_MODE_X_ODD_INC (BIT(6) | BIT(7) | BIT(8))
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#define AR0543_RAW_READ_MODE_Y_ODD_INC (BIT(0) | BIT(1) | BIT(2) |\
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BIT(3) | BIT(4) | BIT(5))
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#define AR0543_RAW_HORIZONTAL_START_H 0x0344
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#define AR0543_RAW_VERTICAL_START_H 0x0346
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#define AR0543_RAW_HORIZONTAL_END_H 0x0348
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#define AR0543_RAW_VERTICAL_END_H 0x034a
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#define AR0543_RAW_HORIZONTAL_OUTPUT_SIZE_H 0x034c
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#define AR0543_RAW_VERTICAL_OUTPUT_SIZE_H 0x034e
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#define AR0543_RAW_COARSE_INTEGRATION_TIME 0x3012
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#define AR0543_RAW_FINE_INTEGRATION_TIME 0x3014
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#define AR0543_RAW_ROW_SPEED 0x3016
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#define AR0543_RAW_GLOBAL_GAIN 0x305e
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#define AR0543_RAW_GLOBAL_GAIN_WR 0x1000
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#define AR0543_RAW_TEST_PATTERN_MODE 0x3070
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#define AR0543_RAW_VCM_SLEW_STEP 0x30F0
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#define AR0543_RAW_VCM_SLEW_STEP_MAX 0x7
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#define AR0543_RAW_VCM_SLEW_STEP_MASK 0x7
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#define AR0543_RAW_VCM_CODE 0x30F2
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#define AR0543_RAW_VCM_SLEW_TIME 0x30F4
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#define AR0543_RAW_VCM_SLEW_TIME_MAX 0xffff
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#define AR0543_RAW_VCM_ENABLE 0x8000
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/* ar0543_raw SCCB */
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#define AR0543_RAW_SCCB_CTRL 0x3100
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#define AR0543_RAW_AEC_PK_EXPO_H 0x3500
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#define AR0543_RAW_AEC_PK_EXPO_M 0x3501
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#define AR0543_RAW_AEC_PK_EXPO_L 0x3502
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#define AR0543_RAW_AEC_MANUAL_CTRL 0x3503
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#define AR0543_RAW_AGC_ADJ_H 0x3508
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#define AR0543_RAW_AGC_ADJ_L 0x3509
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#define AR0543_RAW_FOCAL_LENGTH_NUM 439 /*4.39mm*/
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#define AR0543_RAW_FOCAL_LENGTH_DEM 100
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#define AR0543_RAW_F_NUMBER_DEFAULT_NUM 24
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#define AR0543_RAW_F_NUMBER_DEM 10
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#define AR0543_RAW_X_ADDR_MIN 0X1180
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#define AR0543_RAW_Y_ADDR_MIN 0X1182
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#define AR0543_RAW_X_ADDR_MAX 0X1184
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#define AR0543_RAW_Y_ADDR_MAX 0X1186
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#define AR0543_RAW_MIN_FRAME_LENGTH_LINES 0x1140
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#define AR0543_RAW_MAX_FRAME_LENGTH_LINES 0x1142
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#define AR0543_RAW_MIN_LINE_LENGTH_PCK 0x1144
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#define AR0543_RAW_MAX_LINE_LENGTH_PCK 0x1146
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#define AR0543_RAW_MIN_LINE_BLANKING_PCK 0x1148
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#define AR0543_RAW_MIN_FRAME_BLANKING_LINES 0x114A
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#define AR0543_RAW_X_OUTPUT_SIZE 0x034C
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#define AR0543_RAW_Y_OUTPUT_SIZE 0x034E
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#define AR0543_RAW_BIN_FACTOR_MAX 3
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/*
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* focal length bits definition:
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* bits 31-16: numerator, bits 15-0: denominator
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*/
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#define AR0543_RAW_FOCAL_LENGTH_DEFAULT 0x1B70064
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/*
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* current f-number bits definition:
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* bits 31-16: numerator, bits 15-0: denominator
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*/
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#define AR0543_RAW_F_NUMBER_DEFAULT 0x18000a
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/*
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* f-number range bits definition:
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* bits 31-24: max f-number numerator
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* bits 23-16: max f-number denominator
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* bits 15-8: min f-number numerator
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* bits 7-0: min f-number denominator
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*/
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#define AR0543_RAW_F_NUMBER_RANGE 0x180a180a
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/* Defines for register writes and register array processing */
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#define AR0543_RAW_BYTE_MAX 30
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#define AR0543_RAW_SHORT_MAX 16
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#define I2C_RETRY_COUNT 5
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#define AR0543_RAW_TOK_MASK 0xfff0
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#define AR0543_RAW_STATUS_POWER_DOWN 0x0
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#define AR0543_RAW_STATUS_STANDBY 0x2
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#define AR0543_RAW_STATUS_ACTIVE 0x3
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#define AR0543_RAW_STATUS_VIEWFINDER 0x4
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//ASUS_BSP Wesley, for vcm test
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#define VCM_ADDR 0x0c
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//#define VCM_CODE_MSB 0x03
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//#define VCM_CODE_LSB 0x04
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#define VCM_MAX_FOCUS_POS 1023
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struct s_ctrl_id {
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struct v4l2_queryctrl qc;
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int (*s_ctrl)(struct v4l2_subdev *sd, u32 val);
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int (*g_ctrl)(struct v4l2_subdev *sd, u32 *val);
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};
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enum ar0543_raw_tok_type {
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AR0543_RAW_8BIT = 0x0001,
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AR0543_RAW_16BIT = 0x0002,
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AR0543_RAW_RMW = 0x0010,
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AR0543_RAW_TOK_TERM = 0xf000, /* terminating token for reg list */
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AR0543_RAW_TOK_DELAY = 0xfe00 /* delay token for reg list */
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};
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/*
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* If register address or register width is not 32 bit width,
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* user needs to convert it manually
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*/
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struct s_register_setting {
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u32 reg;
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u32 val;
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};
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struct s_output_format {
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struct v4l2_format v4l2_fmt;
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int fps;
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};
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/**
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* struct ar0543_raw_fwreg - Firmware burst command
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* @type: FW burst or 8/16 bit register
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* @addr: 16-bit offset to register or other values depending on type
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* @val: data value for burst (or other commands)
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*
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* Define a structure for sensor register initialization values
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*/
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struct ar0543_raw_fwreg {
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enum ar0543_raw_tok_type type; /* value, register or FW burst string */
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u16 addr; /* target address */
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u32 val[8];
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};
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/**
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* struct ar0543_raw_reg - MI sensor register format
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* @type: type of the register
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* @reg: 16-bit offset to register
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* @val: 8/16/32-bit register value
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*
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* Define a structure for sensor register initialization values
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*/
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struct ar0543_raw_reg {
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enum ar0543_raw_tok_type type;
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union {
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u16 sreg;
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struct ar0543_raw_fwreg *fwreg;
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} reg;
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u32 val; /* @set value for read/mod/write, @mask */
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u32 val2; /* optional: for rmw, OR mask */
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};
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/* Store macro values' debug names */
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struct macro_string {
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u8 val;
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char *string;
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};
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static inline const char *
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macro_to_string(const struct macro_string *array, int size, u8 val)
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{
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int i;
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for (i = 0; i < size; i++) {
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if (array[i].val == val)
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return array[i].string;
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}
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return "Unknown VAL";
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}
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struct ar0543_raw_control {
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struct v4l2_queryctrl qc;
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int (*query)(struct v4l2_subdev *sd, s32 *value);
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int (*tweak)(struct v4l2_subdev *sd, s32 value);
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};
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struct ar0543_raw_resolution {
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u8 *desc;
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int res;
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int width;
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int height;
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int fps;
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bool used;
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unsigned short pixels_per_line;
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unsigned short lines_per_frame;
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const struct ar0543_raw_reg *regs;
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u8 bin_factor_x;
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u8 bin_factor_y;
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unsigned short skip_frames;
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};
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struct ar0543_raw_format {
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u8 *desc;
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u32 pixelformat;
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struct s_register_setting *regs;
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};
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#define AR0543_DEFAULT_AF_10CM 448
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#define AR0543_DEFAULT_AF_INF 256
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#define AR0543_DEFAULT_AF_START 150
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#define AR0543_DEFAULT_AF_END 700
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struct ar0543_raw_af_data {
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u16 af_inf_pos;
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u16 af_1m_pos;
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u16 af_10cm_pos;
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u16 af_start_curr;
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u8 module_id;
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u8 vendor_id;
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u16 default_af_inf_pos;
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u16 default_af_10cm_pos;
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u16 default_af_start;
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u16 default_af_end;
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};
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#define AR0543_RAW_FUSEID_SIZE 8
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#define AR0543_RAW_FUSEID_START_ADDR 0x31f4
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/* ar0543_raw device structure */
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struct ar0543_raw_device {
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struct v4l2_subdev sd;
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struct media_pad pad;
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struct v4l2_mbus_framefmt format;
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struct camera_sensor_platform_data *platform_data;
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int fmt_idx;
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int status;
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int streaming;
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int power;
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u16 sensor_id;
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u8 sensor_revision;
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u16 coarse_itg;
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u16 fine_itg;
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u16 gain;
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u32 focus;
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u16 pixels_per_line;
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u16 lines_per_frame;
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u8 fps;
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int run_mode;
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struct timespec timestamp_t_focus_abs;
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s16 number_of_steps;
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struct mutex input_lock; /* serialize sensor's ioctl */
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void *otp_data;
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struct ar0543_raw_af_data af_data;
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void *fuseid;
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/* Older VCMs could not maintain the focus position in standby mode. */
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bool keeps_focus_pos;
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struct attribute_group sensor_i2c_attribute; //Add for ATD command+++
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};
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#define AR0543_RAW_MAX_WRITE_BUF_SIZE 32
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struct ar0543_raw_write_buffer {
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u16 addr;
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u8 data[AR0543_RAW_MAX_WRITE_BUF_SIZE];
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};
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struct ar0543_raw_write_ctrl {
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int index;
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struct ar0543_raw_write_buffer buffer;
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};
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#define AR0543_RAW_OTP_READ_EN 0x301A
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#define AR0543_RAW_OTP_TIMING 0x3134
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#define AR0543_RAW_OTP_RECORD_TYPE 0x304C
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#define AR0543_RAW_OTP_AUTO_READ 0x304A
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#define AR0543_RAW_OTP_READY_REG_DONE (1 << 5)
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#define AR0543_RAW_OTP_READY_REG_OK (1 << 6)
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#define AR0543_RAW_OTP_AF_INF_POS_H 0x3800
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#define AR0543_RAW_OTP_AF_INF_POS_L 0x3801
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#define AR0543_RAW_OTP_AF_1M_POS 0x3802
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#define AR0543_RAW_OTP_AF_10CM_POS 0x3804
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#define AR0543_RAW_OTP_AF_START_CURR 0x3806
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#define AR0543_RAW_OTP_AF_MODULE_ID 0x3808
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#define AR0543_RAW_OTP_AF_VENDOR_ID 0x3809
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#define AR0543_RAW_OTP_DATA_SIZE 0x60
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#define GROUPED_PARAMETER_HOLD_ENABLE {AR0543_RAW_8BIT, {0x0104}, 0x1}
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#define GROUPED_PARAMETER_HOLD_DISABLE {AR0543_RAW_8BIT, {0x0104}, 0x0}
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#define INIT_VCM_CONTROL {AR0543_RAW_16BIT, {0x30F0}, 0x800C} /* slew_rate[2:0] */
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static const struct ar0543_raw_reg ar0543_raw_init_vcm[] = {
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INIT_VCM_CONTROL, /* VCM_CONTROL */
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{AR0543_RAW_16BIT, {0x30F2}, 0x0000}, /* VCM_NEW_CODE */
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{AR0543_RAW_16BIT, {0x30F4}, 0x0080}, /* VCM_STEP_TIME */
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{AR0543_RAW_TOK_TERM, {0}, 0}
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};
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//#define RESET_REGISTER {AR0543_RAW_16BIT, {0x301A}, 0x4A38}
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static const struct ar0543_raw_reg ar0543_raw_reset_register[] = {
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{AR0543_RAW_8BIT,{0x0103},0x01}, //SOFTWARE_RESET (clears itself)
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{AR0543_RAW_TOK_DELAY, {0}, 50}, //DELAY=50 //Initialization Time
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//stop_streaming
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{AR0543_RAW_8BIT,{0x0100},0x00},// MODE_SELECT
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//dual_lane_MIPI_interface
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{AR0543_RAW_16BIT,{0x301A},0x0618},// RESET_REGISTER
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{AR0543_RAW_16BIT,{0x3064},0xB800},// SMIA_TEST
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{AR0543_RAW_16BIT,{0x31AE},0x0202},// SERIAL_FORMAT
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{AR0543_RAW_16BIT,{0x0112},0x0A0A},// 10bit raw output
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//REV1_recommended_settings
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{AR0543_RAW_16BIT,{0x316A},0x8400},// DAC_FBIAS
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{AR0543_RAW_16BIT,{0x316C},0x8400},// DAC_TXLO
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{AR0543_RAW_16BIT,{0x316E},0x8400},// DAC_ECL
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{AR0543_RAW_16BIT,{0x3EFA},0x1A1F},// DAC_LD_ECL
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{AR0543_RAW_16BIT,{0x3ED2},0xD965},// DAC_LD_6_7
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{AR0543_RAW_16BIT,{0x3ED8},0x7F1B},// DAC_LD_12_13
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{AR0543_RAW_16BIT,{0x3EDA},0x2F11},// DAC_LD_14_15
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{AR0543_RAW_16BIT,{0x3EE2},0x0060},// DAC_LD_22_23
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{AR0543_RAW_16BIT,{0x3EF2},0xD965},// DAC_LP_6_7
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{AR0543_RAW_16BIT,{0x3EF8},0x797F},// DAC_LD_TXHI
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{AR0543_RAW_16BIT,{0x3EFC},0x286F},// DAC_LD_FBIAS
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{AR0543_RAW_16BIT,{0x3EFE},0x2C01},// DAC_LD_TXLO
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//REV1_pixel_timing
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{AR0543_RAW_16BIT,{0x3E00},0x042F},// DYNAMIC_SEQRAM_00
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{AR0543_RAW_16BIT,{0x3E02},0xFFFF},// DYNAMIC_SEQRAM_02
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{AR0543_RAW_16BIT,{0x3E04},0xFFFF},// DYNAMIC_SEQRAM_04
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{AR0543_RAW_16BIT,{0x3E06},0xFFFF},// DYNAMIC_SEQRAM_06
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{AR0543_RAW_16BIT,{0x3E08},0x8071},// DYNAMIC_SEQRAM_08
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{AR0543_RAW_16BIT,{0x3E0A},0x7281},// DYNAMIC_SEQRAM_0A
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{AR0543_RAW_16BIT,{0x3E0C},0x4011},// DYNAMIC_SEQRAM_0C
|
|
{AR0543_RAW_16BIT,{0x3E0E},0x8010},// DYNAMIC_SEQRAM_0E
|
|
{AR0543_RAW_16BIT,{0x3E10},0x60A5},// DYNAMIC_SEQRAM_10
|
|
{AR0543_RAW_16BIT,{0x3E12},0x4080},// DYNAMIC_SEQRAM_12
|
|
{AR0543_RAW_16BIT,{0x3E14},0x4180},// DYNAMIC_SEQRAM_14
|
|
{AR0543_RAW_16BIT,{0x3E16},0x0018},// DYNAMIC_SEQRAM_16
|
|
{AR0543_RAW_16BIT,{0x3E18},0x46B7},// DYNAMIC_SEQRAM_18
|
|
{AR0543_RAW_16BIT,{0x3E1A},0x4994},// DYNAMIC_SEQRAM_1A
|
|
{AR0543_RAW_16BIT,{0x3E1C},0x4997},// DYNAMIC_SEQRAM_1C
|
|
{AR0543_RAW_16BIT,{0x3E1E},0x4682},// DYNAMIC_SEQRAM_1E
|
|
{AR0543_RAW_16BIT,{0x3E20},0x0018},// DYNAMIC_SEQRAM_20
|
|
{AR0543_RAW_16BIT,{0x3E22},0x4241},// DYNAMIC_SEQRAM_22
|
|
{AR0543_RAW_16BIT,{0x3E24},0x8000},// DYNAMIC_SEQRAM_24
|
|
{AR0543_RAW_16BIT,{0x3E26},0x1880},// DYNAMIC_SEQRAM_26
|
|
{AR0543_RAW_16BIT,{0x3E28},0x4785},// DYNAMIC_SEQRAM_28
|
|
{AR0543_RAW_16BIT,{0x3E2A},0x4992},// DYNAMIC_SEQRAM_2A
|
|
{AR0543_RAW_16BIT,{0x3E2C},0x4997},// DYNAMIC_SEQRAM_2C
|
|
{AR0543_RAW_16BIT,{0x3E2E},0x4780},// DYNAMIC_SEQRAM_2E
|
|
{AR0543_RAW_16BIT,{0x3E30},0x4D80},// DYNAMIC_SEQRAM_30
|
|
{AR0543_RAW_16BIT,{0x3E32},0x100C},// DYNAMIC_SEQRAM_32
|
|
{AR0543_RAW_16BIT,{0x3E34},0x8000},// DYNAMIC_SEQRAM_34
|
|
{AR0543_RAW_16BIT,{0x3E36},0x184A},// DYNAMIC_SEQRAM_36
|
|
{AR0543_RAW_16BIT,{0x3E38},0x8042},// DYNAMIC_SEQRAM_38
|
|
{AR0543_RAW_16BIT,{0x3E3A},0x001A},// DYNAMIC_SEQRAM_3A
|
|
{AR0543_RAW_16BIT,{0x3E3C},0x9610},// DYNAMIC_SEQRAM_3C
|
|
{AR0543_RAW_16BIT,{0x3E3E},0x0C80},// DYNAMIC_SEQRAM_3E
|
|
{AR0543_RAW_16BIT,{0x3E40},0x4DC6},// DYNAMIC_SEQRAM_40
|
|
{AR0543_RAW_16BIT,{0x3E42},0x4A80},// DYNAMIC_SEQRAM_42
|
|
{AR0543_RAW_16BIT,{0x3E44},0x0018},// DYNAMIC_SEQRAM_44
|
|
{AR0543_RAW_16BIT,{0x3E46},0x8042},// DYNAMIC_SEQRAM_46
|
|
{AR0543_RAW_16BIT,{0x3E48},0x8041},// DYNAMIC_SEQRAM_48
|
|
{AR0543_RAW_16BIT,{0x3E4A},0x0018},// DYNAMIC_SEQRAM_4A
|
|
{AR0543_RAW_16BIT,{0x3E4C},0x804B},// DYNAMIC_SEQRAM_4C
|
|
{AR0543_RAW_16BIT,{0x3E4E},0xB74B},// DYNAMIC_SEQRAM_4E
|
|
{AR0543_RAW_16BIT,{0x3E50},0x8010},// DYNAMIC_SEQRAM_50
|
|
{AR0543_RAW_16BIT,{0x3E52},0x6056},// DYNAMIC_SEQRAM_52
|
|
{AR0543_RAW_16BIT,{0x3E54},0x001C},// DYNAMIC_SEQRAM_54
|
|
{AR0543_RAW_16BIT,{0x3E56},0x8211},// DYNAMIC_SEQRAM_56
|
|
{AR0543_RAW_16BIT,{0x3E58},0x8056},// DYNAMIC_SEQRAM_58
|
|
{AR0543_RAW_16BIT,{0x3E5A},0x827C},// DYNAMIC_SEQRAM_5A
|
|
{AR0543_RAW_16BIT,{0x3E5C},0x0970},// DYNAMIC_SEQRAM_5C
|
|
{AR0543_RAW_16BIT,{0x3E5E},0x8082},// DYNAMIC_SEQRAM_5E
|
|
{AR0543_RAW_16BIT,{0x3E60},0x7281},// DYNAMIC_SEQRAM_60
|
|
{AR0543_RAW_16BIT,{0x3E62},0x4C40},// DYNAMIC_SEQRAM_62
|
|
{AR0543_RAW_16BIT,{0x3E64},0x8E4D},// DYNAMIC_SEQRAM_64
|
|
{AR0543_RAW_16BIT,{0x3E66},0x8110},// DYNAMIC_SEQRAM_66
|
|
{AR0543_RAW_16BIT,{0x3E68},0x0CAF},// DYNAMIC_SEQRAM_68
|
|
{AR0543_RAW_16BIT,{0x3E6A},0x4D80},// DYNAMIC_SEQRAM_6A
|
|
{AR0543_RAW_16BIT,{0x3E6C},0x100C},// DYNAMIC_SEQRAM_6C
|
|
{AR0543_RAW_16BIT,{0x3E6E},0x8440},// DYNAMIC_SEQRAM_6E
|
|
{AR0543_RAW_16BIT,{0x3E70},0x4C81},// DYNAMIC_SEQRAM_70
|
|
{AR0543_RAW_16BIT,{0x3E72},0x7C5F},// DYNAMIC_SEQRAM_72
|
|
{AR0543_RAW_16BIT,{0x3E74},0x7000},// DYNAMIC_SEQRAM_74
|
|
{AR0543_RAW_16BIT,{0x3E76},0x0000},// DYNAMIC_SEQRAM_76
|
|
{AR0543_RAW_16BIT,{0x3E78},0x0000},// DYNAMIC_SEQRAM_78
|
|
{AR0543_RAW_16BIT,{0x3E7A},0x0000},// DYNAMIC_SEQRAM_7A
|
|
{AR0543_RAW_16BIT,{0x3E7C},0x0000},// DYNAMIC_SEQRAM_7C
|
|
{AR0543_RAW_16BIT,{0x3E7E},0x0000},// DYNAMIC_SEQRAM_7E
|
|
{AR0543_RAW_16BIT,{0x3E80},0x0000},// DYNAMIC_SEQRAM_80
|
|
{AR0543_RAW_16BIT,{0x3E82},0x0000},// DYNAMIC_SEQRAM_82
|
|
{AR0543_RAW_16BIT,{0x3E84},0x0000},// DYNAMIC_SEQRAM_84
|
|
{AR0543_RAW_16BIT,{0x3E86},0x0000},// DYNAMIC_SEQRAM_86
|
|
{AR0543_RAW_16BIT,{0x3E88},0x0000},// DYNAMIC_SEQRAM_88
|
|
{AR0543_RAW_16BIT,{0x3E8A},0x0000},// DYNAMIC_SEQRAM_8A
|
|
{AR0543_RAW_16BIT,{0x3E8C},0x0000},// DYNAMIC_SEQRAM_8C
|
|
{AR0543_RAW_16BIT,{0x3E8E},0x0000},// DYNAMIC_SEQRAM_8E
|
|
{AR0543_RAW_16BIT,{0x3E90},0x0000},// DYNAMIC_SEQRAM_90
|
|
{AR0543_RAW_16BIT,{0x3E92},0x0000},// DYNAMIC_SEQRAM_92
|
|
{AR0543_RAW_16BIT,{0x3E94},0x0000},// DYNAMIC_SEQRAM_94
|
|
{AR0543_RAW_16BIT,{0x3E96},0x0000},// DYNAMIC_SEQRAM_96
|
|
{AR0543_RAW_16BIT,{0x3E98},0x0000},// DYNAMIC_SEQRAM_98
|
|
{AR0543_RAW_16BIT,{0x3E9A},0x0000},// DYNAMIC_SEQRAM_9A
|
|
{AR0543_RAW_16BIT,{0x3E9C},0x0000},// DYNAMIC_SEQRAM_9C
|
|
{AR0543_RAW_16BIT,{0x3E9E},0x0000},// DYNAMIC_SEQRAM_9E
|
|
{AR0543_RAW_16BIT,{0x3EA0},0x0000},// DYNAMIC_SEQRAM_A0
|
|
{AR0543_RAW_16BIT,{0x3EA2},0x0000},// DYNAMIC_SEQRAM_A2
|
|
{AR0543_RAW_16BIT,{0x3EA4},0x0000},// DYNAMIC_SEQRAM_A4
|
|
{AR0543_RAW_16BIT,{0x3EA6},0x0000},// DYNAMIC_SEQRAM_A6
|
|
{AR0543_RAW_16BIT,{0x3EA8},0x0000},// DYNAMIC_SEQRAM_A8
|
|
{AR0543_RAW_16BIT,{0x3EAA},0x0000},// DYNAMIC_SEQRAM_AA
|
|
{AR0543_RAW_16BIT,{0x3EAC},0x0000},// DYNAMIC_SEQRAM_AC
|
|
{AR0543_RAW_16BIT,{0x3EAE},0x0000},// DYNAMIC_SEQRAM_AE
|
|
{AR0543_RAW_16BIT,{0x3EB0},0x0000},// DYNAMIC_SEQRAM_B0
|
|
{AR0543_RAW_16BIT,{0x3EB2},0x0000},// DYNAMIC_SEQRAM_B2
|
|
{AR0543_RAW_16BIT,{0x3EB4},0x0000},// DYNAMIC_SEQRAM_B4
|
|
{AR0543_RAW_16BIT,{0x3EB6},0x0000},// DYNAMIC_SEQRAM_B6
|
|
{AR0543_RAW_16BIT,{0x3EB8},0x0000},// DYNAMIC_SEQRAM_B8
|
|
{AR0543_RAW_16BIT,{0x3EBA},0x0000},// DYNAMIC_SEQRAM_BA
|
|
{AR0543_RAW_16BIT,{0x3EBC},0x0000},// DYNAMIC_SEQRAM_BC
|
|
{AR0543_RAW_16BIT,{0x3EBE},0x0000},// DYNAMIC_SEQRAM_BE
|
|
{AR0543_RAW_16BIT,{0x3EC0},0x0000},// DYNAMIC_SEQRAM_C0
|
|
{AR0543_RAW_16BIT,{0x3EC2},0x0000},// DYNAMIC_SEQRAM_C2
|
|
{AR0543_RAW_16BIT,{0x3EC4},0x0000},// DYNAMIC_SEQRAM_C4
|
|
{AR0543_RAW_16BIT,{0x3EC6},0x0000},// DYNAMIC_SEQRAM_C6
|
|
{AR0543_RAW_16BIT,{0x3EC8},0x0000},// DYNAMIC_SEQRAM_C8
|
|
{AR0543_RAW_16BIT,{0x3ECA},0x0000},// DYNAMIC_SEQRAM_CA
|
|
{AR0543_RAW_16BIT,{0x3170},0x2150},// ANALOG_CONTROL
|
|
{AR0543_RAW_16BIT,{0x317A},0x0150},// ANALOG_CONTROL6
|
|
{AR0543_RAW_16BIT,{0x3ECC},0x2200},// DAC_LD_0_1
|
|
{AR0543_RAW_16BIT,{0x3174},0x0000},// ANALOG_CONTROL3
|
|
{AR0543_RAW_16BIT,{0x3176},0x0000},// ANALOG_CONTROL4
|
|
{AR0543_RAW_16BIT,{0x30BC},0x0384},// CALIB_GLOBAL
|
|
{AR0543_RAW_16BIT,{0x30C0},0x1220},// CALIB_CONTROL
|
|
{AR0543_RAW_16BIT,{0x30D4},0x9200},// COLUMN_CORRECTION
|
|
{AR0543_RAW_16BIT,{0x30B2},0xC000},// CALIB_TIED_OFFSET
|
|
|
|
{AR0543_RAW_16BIT,{0x31B0},0x00C4},// FRAME_PREAMBLE
|
|
{AR0543_RAW_16BIT,{0x31B2},0x0064},// LINE_PREAMBLE
|
|
|
|
|
|
{AR0543_RAW_16BIT,{0x31B4},0x0E77},// MIPI_TIMING_0
|
|
{AR0543_RAW_16BIT,{0x31B6},0x0D24},// MIPI_TIMING_1
|
|
{AR0543_RAW_16BIT,{0x31B8},0x020E},// MIPI_TIMING_2
|
|
{AR0543_RAW_16BIT,{0x31BA},0x0710},// MIPI_TIMING_3
|
|
{AR0543_RAW_16BIT,{0x31BC},0x2A0D},// MIPI_TIMING_4
|
|
{AR0543_RAW_16BIT,{0x31BE},0xC003},// MIPI_CONFIG_STATUS
|
|
|
|
//updated June 2013--ADACD and 2DDC settings
|
|
//ADACD: low gain
|
|
#ifdef CONFIG_ME175CG
|
|
{AR0543_RAW_16BIT,{0x3100},0x0002},// ADACD_CONTROL
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3100},0x0000},// ADACD_CONTROL //denoise off
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3102},0x0064},// ADACD_NOISE_MODEL1
|
|
{AR0543_RAW_16BIT,{0x3104},0x0B6D},// ADACD_NOISE_MODEL2
|
|
{AR0543_RAW_16BIT,{0x3106},0x0201},// ADACD_NOISE_FLOOR1
|
|
{AR0543_RAW_16BIT,{0x3108},0x0905},// ADACD_NOISE_FLOOR2
|
|
{AR0543_RAW_16BIT,{0x310A},0x002A},// ADACD_PEDESTAL
|
|
//2DDC: low gain
|
|
{AR0543_RAW_16BIT,{0x31E0},0x1F01},// PIX_DEF_ID
|
|
{AR0543_RAW_16BIT,{0x3F02},0x0001},// PIX_DEF_2D_DDC_THRESH_HI3
|
|
{AR0543_RAW_16BIT,{0x3F04},0x0032},// PIX_DEF_2D_DDC_THRESH_LO3
|
|
{AR0543_RAW_16BIT,{0x3F06},0x015E},// PIX_DEF_2D_DDC_THRESH_HI4
|
|
{AR0543_RAW_16BIT,{0x3F08},0x0190},// PIX_DEF_2D_DDC_THRESH_LO4
|
|
|
|
{AR0543_RAW_16BIT,{0x305E},0x1127},// GLOBAL_GAIN
|
|
|
|
//Smaller_FallOff60+++
|
|
{AR0543_RAW_16BIT,{0x3780}, 0x0000},
|
|
{AR0543_RAW_16BIT,{0x3600}, 0x0110},
|
|
{AR0543_RAW_16BIT,{0x3602}, 0x1F89},
|
|
{AR0543_RAW_16BIT,{0x3604}, 0x02D1},
|
|
{AR0543_RAW_16BIT,{0x3606}, 0xC2CD},
|
|
{AR0543_RAW_16BIT,{0x3608}, 0xACB1},
|
|
{AR0543_RAW_16BIT,{0x360A}, 0x02B0},
|
|
{AR0543_RAW_16BIT,{0x360C}, 0x096C},
|
|
{AR0543_RAW_16BIT,{0x360E}, 0x5870},
|
|
{AR0543_RAW_16BIT,{0x3610}, 0x80EC},
|
|
{AR0543_RAW_16BIT,{0x3612}, 0xC111},
|
|
{AR0543_RAW_16BIT,{0x3614}, 0x0250},
|
|
{AR0543_RAW_16BIT,{0x3616}, 0x2A08},
|
|
{AR0543_RAW_16BIT,{0x3618}, 0x1AD0},
|
|
{AR0543_RAW_16BIT,{0x361A}, 0xCF2E},
|
|
{AR0543_RAW_16BIT,{0x361C}, 0x8E71},
|
|
{AR0543_RAW_16BIT,{0x361E}, 0x0370},
|
|
{AR0543_RAW_16BIT,{0x3620}, 0xF14B},
|
|
{AR0543_RAW_16BIT,{0x3622}, 0x0E51},
|
|
{AR0543_RAW_16BIT,{0x3624}, 0xCCCB},
|
|
{AR0543_RAW_16BIT,{0x3626}, 0xD251},
|
|
{AR0543_RAW_16BIT,{0x3640}, 0xA8AB},
|
|
{AR0543_RAW_16BIT,{0x3642}, 0x9B8D},
|
|
{AR0543_RAW_16BIT,{0x3644}, 0xD2CE},
|
|
{AR0543_RAW_16BIT,{0x3646}, 0xA76B},
|
|
{AR0543_RAW_16BIT,{0x3648}, 0x1C70},
|
|
{AR0543_RAW_16BIT,{0x364A}, 0x5069},
|
|
{AR0543_RAW_16BIT,{0x364C}, 0x242E},
|
|
{AR0543_RAW_16BIT,{0x364E}, 0xAA8A},
|
|
{AR0543_RAW_16BIT,{0x3650}, 0xAE0F},
|
|
{AR0543_RAW_16BIT,{0x3652}, 0xC76D},
|
|
{AR0543_RAW_16BIT,{0x3654}, 0x562A},
|
|
{AR0543_RAW_16BIT,{0x3656}, 0x7BCD},
|
|
{AR0543_RAW_16BIT,{0x3658}, 0x702D},
|
|
{AR0543_RAW_16BIT,{0x365A}, 0xCA6E},
|
|
{AR0543_RAW_16BIT,{0x365C}, 0x9CEE},
|
|
{AR0543_RAW_16BIT,{0x365E}, 0xF287},
|
|
{AR0543_RAW_16BIT,{0x3660}, 0xA10E},
|
|
{AR0543_RAW_16BIT,{0x3662}, 0x78EE},
|
|
{AR0543_RAW_16BIT,{0x3664}, 0x11CE},
|
|
{AR0543_RAW_16BIT,{0x3666}, 0x962F},
|
|
{AR0543_RAW_16BIT,{0x3680}, 0x03D1},
|
|
{AR0543_RAW_16BIT,{0x3682}, 0x16AE},
|
|
{AR0543_RAW_16BIT,{0x3684}, 0xA2D1},
|
|
{AR0543_RAW_16BIT,{0x3686}, 0xD8CF},
|
|
{AR0543_RAW_16BIT,{0x3688}, 0x8EF3},
|
|
{AR0543_RAW_16BIT,{0x368A}, 0x15D1},
|
|
{AR0543_RAW_16BIT,{0x368C}, 0x9BAE},
|
|
{AR0543_RAW_16BIT,{0x368E}, 0xBF32},
|
|
{AR0543_RAW_16BIT,{0x3690}, 0xB910},
|
|
{AR0543_RAW_16BIT,{0x3692}, 0x244E},
|
|
{AR0543_RAW_16BIT,{0x3694}, 0x5F30},
|
|
{AR0543_RAW_16BIT,{0x3696}, 0x128C},
|
|
{AR0543_RAW_16BIT,{0x3698}, 0xA6D2},
|
|
{AR0543_RAW_16BIT,{0x369A}, 0x2EEF},
|
|
{AR0543_RAW_16BIT,{0x369C}, 0x0611},
|
|
{AR0543_RAW_16BIT,{0x369E}, 0x0631},
|
|
{AR0543_RAW_16BIT,{0x36A0}, 0xFC8D},
|
|
{AR0543_RAW_16BIT,{0x36A2}, 0xBE51},
|
|
{AR0543_RAW_16BIT,{0x36A4}, 0x80B0},
|
|
{AR0543_RAW_16BIT,{0x36A6}, 0xED52},
|
|
{AR0543_RAW_16BIT,{0x36C0}, 0x8FAD},
|
|
{AR0543_RAW_16BIT,{0x36C2}, 0xC2CB},
|
|
{AR0543_RAW_16BIT,{0x36C4}, 0x6710},
|
|
{AR0543_RAW_16BIT,{0x36C6}, 0x26F0},
|
|
{AR0543_RAW_16BIT,{0x36C8}, 0xCF91},
|
|
{AR0543_RAW_16BIT,{0x36CA}, 0x456E},
|
|
{AR0543_RAW_16BIT,{0x36CC}, 0xC0AE},
|
|
{AR0543_RAW_16BIT,{0x36CE}, 0xA5F0},
|
|
{AR0543_RAW_16BIT,{0x36D0}, 0x156F},
|
|
{AR0543_RAW_16BIT,{0x36D2}, 0x18D1},
|
|
{AR0543_RAW_16BIT,{0x36D4}, 0xAEED},
|
|
{AR0543_RAW_16BIT,{0x36D6}, 0xA6CE},
|
|
{AR0543_RAW_16BIT,{0x36D8}, 0x178E},
|
|
{AR0543_RAW_16BIT,{0x36DA}, 0x140C},
|
|
{AR0543_RAW_16BIT,{0x36DC}, 0xB40E},
|
|
{AR0543_RAW_16BIT,{0x36DE}, 0x85AB},
|
|
{AR0543_RAW_16BIT,{0x36E0}, 0x216E},
|
|
{AR0543_RAW_16BIT,{0x36E2}, 0x23CE},
|
|
{AR0543_RAW_16BIT,{0x36E4}, 0x6E2E},
|
|
{AR0543_RAW_16BIT,{0x36E6}, 0xBEAF},
|
|
{AR0543_RAW_16BIT,{0x3700}, 0x9CF1},
|
|
{AR0543_RAW_16BIT,{0x3702}, 0xAD4F},
|
|
{AR0543_RAW_16BIT,{0x3704}, 0x8154},
|
|
{AR0543_RAW_16BIT,{0x3706}, 0x6550},
|
|
{AR0543_RAW_16BIT,{0x3708}, 0x2DD5},
|
|
{AR0543_RAW_16BIT,{0x370A}, 0xF791},
|
|
{AR0543_RAW_16BIT,{0x370C}, 0xFD6E},
|
|
{AR0543_RAW_16BIT,{0x370E}, 0xF411},
|
|
{AR0543_RAW_16BIT,{0x3710}, 0x2272},
|
|
{AR0543_RAW_16BIT,{0x3712}, 0x1E94},
|
|
{AR0543_RAW_16BIT,{0x3714}, 0xBC11},
|
|
{AR0543_RAW_16BIT,{0x3716}, 0x860E},
|
|
{AR0543_RAW_16BIT,{0x3718}, 0x898F},
|
|
{AR0543_RAW_16BIT,{0x371A}, 0xAACF},
|
|
{AR0543_RAW_16BIT,{0x371C}, 0x3072},
|
|
{AR0543_RAW_16BIT,{0x371E}, 0x96D1},
|
|
{AR0543_RAW_16BIT,{0x3720}, 0xE84D},
|
|
{AR0543_RAW_16BIT,{0x3722}, 0x8454},
|
|
{AR0543_RAW_16BIT,{0x3724}, 0x0DD2},
|
|
{AR0543_RAW_16BIT,{0x3726}, 0x2C95},
|
|
{AR0543_RAW_16BIT,{0x3782}, 0x0544},
|
|
{AR0543_RAW_16BIT,{0x3784}, 0x03B4},
|
|
{AR0543_RAW_16BIT,{0x37C0}, 0x0000},
|
|
{AR0543_RAW_16BIT,{0x37C2}, 0x0000},
|
|
{AR0543_RAW_16BIT,{0x37C4}, 0x0000},
|
|
{AR0543_RAW_16BIT,{0x37C6}, 0x0000},
|
|
{AR0543_RAW_16BIT,{0x3780}, 0x8000},
|
|
//Smaller_FallOff60---
|
|
|
|
{AR0543_RAW_16BIT,{0x3ECE},0x000A},// DAC_LD_2_3
|
|
{AR0543_RAW_16BIT,{0x0400},0x0000},// SCALING_MODE
|
|
{AR0543_RAW_16BIT,{0x0404},0x0010},// SCALE_M
|
|
|
|
//PLL_Configuration
|
|
{AR0543_RAW_16BIT,{0x0300},0x06},//vt_pix_clk_div = 0x6
|
|
{AR0543_RAW_16BIT,{0x0302},0x01},//vt_sys_clk_div = 0x1
|
|
{AR0543_RAW_16BIT,{0x0304},0x02},//pre_pll_clk_div = 0x2
|
|
{AR0543_RAW_16BIT,{0x0306},0x46},//pll_multiplier = 0x46
|
|
{AR0543_RAW_16BIT,{0x0308},0x0A},//op_pix_clk_div = 0xA
|
|
{AR0543_RAW_16BIT,{0x030A},0x01},//op_sys_clk_div = 0x1
|
|
{AR0543_RAW_TOK_DELAY, {0}, 5},//DELAY=5
|
|
|
|
//2592*1944 @15FPS
|
|
{AR0543_RAW_16BIT,{0x0400}, 0x0000}, //scaling_mode
|
|
{AR0543_RAW_16BIT,{0x0404}, 0x0010}, //scale_m
|
|
{AR0543_RAW_16BIT,{0x034C}, 0x0A20}, //Output Width
|
|
{AR0543_RAW_16BIT,{0x034E}, 0x0798}, //Output Height
|
|
{AR0543_RAW_16BIT,{0x0344}, 0x0008}, //Column Start
|
|
{AR0543_RAW_16BIT,{0x0346}, 0x0008}, //Row Start
|
|
{AR0543_RAW_16BIT,{0x0348}, 0x0A27}, //Column End
|
|
{AR0543_RAW_16BIT,{0x034A}, 0x079F}, //Row End
|
|
#ifdef CONFIG_ME175CG
|
|
{AR0543_RAW_16BIT,{0x3040}, 0xC041}, //Read Mode
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3040}, 0x0041}, //Read Mode
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3010}, 0x00A0}, //Fine Correction
|
|
{AR0543_RAW_16BIT,{0x3012}, 0x07E4}, //Coarse Integration Time
|
|
{AR0543_RAW_16BIT,{0x3014}, 0x02CE}, //Fine Integration Time
|
|
{AR0543_RAW_16BIT,{0x0340}, 0x07E5}, //Frame Lines
|
|
{AR0543_RAW_16BIT,{0x0342}, 0x0E6E}, //Line Length
|
|
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x00 }, // GROUPED_PARAMETER_HOLD
|
|
|
|
//=== End of Initial Setting ===
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static const struct ar0543_raw_reg ar0543_raw_soft_standby[] = {
|
|
{AR0543_RAW_8BIT, {0x0100}, 0x00},
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static const struct ar0543_raw_reg ar0543_raw_streaming[] = {
|
|
{AR0543_RAW_8BIT, {0x0100}, 0x01},
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static const struct ar0543_raw_reg ar0543_raw_param_hold[] = {
|
|
{AR0543_RAW_8BIT, {0x0104}, 0x01}, /* GROUPED_PARAMETER_HOLD */
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static const struct ar0543_raw_reg ar0543_raw_param_update[] = {
|
|
{AR0543_RAW_8BIT, {0x0104}, 0x00}, /* GROUPED_PARAMETER_HOLD */
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
|
|
static struct ar0543_raw_reg const ar0543_raw_2592x1944_15fps[] = {
|
|
//[2592*1944 @15FPS]
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x01}, // GROUPED_PARAMETER_HOLD = 0x1
|
|
|
|
// Timing Settings
|
|
{AR0543_RAW_16BIT,{0x0400}, 0x0000}, // scaling_mode
|
|
{AR0543_RAW_16BIT,{0x0404}, 0x0010}, // scale_m
|
|
{AR0543_RAW_16BIT,{0x034C}, 0x0A20}, // Output Width
|
|
{AR0543_RAW_16BIT,{0x034E}, 0x0798}, // Output Height
|
|
{AR0543_RAW_16BIT,{0x0344}, 0x0008}, // Column Start
|
|
{AR0543_RAW_16BIT,{0x0346}, 0x0008}, // Row Start
|
|
{AR0543_RAW_16BIT,{0x0348}, 0x0A27}, // Column End
|
|
{AR0543_RAW_16BIT,{0x034A}, 0x079F}, // Row End
|
|
#ifdef CONFIG_ME175CG
|
|
{AR0543_RAW_16BIT,{0x3040}, 0xC041}, //Read Mode
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3040}, 0x0041}, //Read Mode
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3010}, 0x00A0}, // Fine Correction
|
|
{AR0543_RAW_16BIT,{0x3012}, 0x07E4}, // Coarse Integration Time
|
|
{AR0543_RAW_16BIT,{0x3014}, 0x02CE}, // Fine Integration Time
|
|
{AR0543_RAW_16BIT,{0x0340}, 0x07E5}, // Frame Lines
|
|
{AR0543_RAW_16BIT,{0x0342}, 0x0E6E}, // Line Length
|
|
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x00}, // GROUPED_PARAMETER_HOLD
|
|
{AR0543_RAW_TOK_DELAY, {0}, 5},//DELAY=5
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static struct ar0543_raw_reg const ar0543_raw_1080p_30fps[] = {
|
|
//[1936*1096 @30FPS]
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x01}, // GROUPED_PARAMETER_HOLD = 0x1
|
|
|
|
// Timing Settings
|
|
{AR0543_RAW_16BIT,{0x0400}, 0x0000}, // scaling_mode
|
|
{AR0543_RAW_16BIT,{0x0404}, 0x0010}, // scale_m
|
|
{AR0543_RAW_16BIT,{0x034C}, 0x0790}, // Output Width
|
|
{AR0543_RAW_16BIT,{0x034E}, 0x0448}, // Output Height
|
|
{AR0543_RAW_16BIT,{0x0344}, 0x0008}, // Column Start
|
|
{AR0543_RAW_16BIT,{0x0346}, 0x0008}, // Row Start
|
|
{AR0543_RAW_16BIT,{0x0348}, 0x0797}, // Column End
|
|
{AR0543_RAW_16BIT,{0x034A}, 0x044F}, // Row End
|
|
#ifdef CONFIG_ME175CG
|
|
|
|
{AR0543_RAW_16BIT,{0x3040}, 0xC041}, //Read Mode
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3040}, 0x0041}, //Read Mode
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3010}, 0x00A0}, // Fine Correction
|
|
{AR0543_RAW_16BIT,{0x3012}, 0x058E}, // Coarse Integration Time
|
|
{AR0543_RAW_16BIT,{0x3014}, 0x02CE}, // Fine Integration Time
|
|
{AR0543_RAW_16BIT,{0x0340}, 0x058F}, // Frame Lines
|
|
{AR0543_RAW_16BIT,{0x0342}, 0x0BE0}, // Line Length
|
|
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x00}, // GROUPED_PARAMETER_HOLD
|
|
{AR0543_RAW_TOK_DELAY, {0}, 5},//DELAY=5
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static struct ar0543_raw_reg const ar0543_raw_960p_30fps[] = {
|
|
//[1296*976 @30FPS]
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x01}, // GROUPED_PARAMETER_HOLD = 0x1
|
|
|
|
// Timing Settings
|
|
{AR0543_RAW_16BIT,{0x0400}, 0x0000}, // scaling_mode
|
|
{AR0543_RAW_16BIT,{0x0404}, 0x0010}, // scale_m
|
|
{AR0543_RAW_16BIT,{0x034C}, 0x0510}, // Output Width
|
|
{AR0543_RAW_16BIT,{0x034E}, 0x03D0}, // Output Height
|
|
{AR0543_RAW_16BIT,{0x0344}, 0x0008}, // Column Start
|
|
{AR0543_RAW_16BIT,{0x0346}, 0x0008}, // Row Start
|
|
{AR0543_RAW_16BIT,{0x0348}, 0x0A25}, // Column End
|
|
{AR0543_RAW_16BIT,{0x034A}, 0x07A5}, // Row End
|
|
#ifdef CONFIG_ME175CG
|
|
{AR0543_RAW_16BIT,{0x3040}, 0xC4C3}, //Read Mode
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3040}, 0x04C3}, //Read Mode
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3010}, 0x0184}, // Fine Correction
|
|
{AR0543_RAW_16BIT,{0x3012}, 0x04F5}, // Coarse Integration Time
|
|
{AR0543_RAW_16BIT,{0x3014}, 0x05F8}, // Fine Integration Time
|
|
{AR0543_RAW_16BIT,{0x0340}, 0x04F6}, // Frame Lines
|
|
{AR0543_RAW_16BIT,{0x0342}, 0x0C4E}, // Line Length
|
|
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x00}, // GROUPED_PARAMETER_HOLD
|
|
{AR0543_RAW_TOK_DELAY, {0}, 5},//DELAY=5
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
|
|
static struct ar0543_raw_reg const ar0543_raw_720p_30fps[] = {
|
|
//[1296*736 @30FPS]
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x01}, // GROUPED_PARAMETER_HOLD = 0x1
|
|
|
|
// Timing Settings
|
|
{AR0543_RAW_16BIT,{0x0400}, 0x0000}, // scaling_mode
|
|
{AR0543_RAW_16BIT,{0x0404}, 0x0010}, // scale_m
|
|
{AR0543_RAW_16BIT,{0x034C}, 0x0510}, // Output Width
|
|
{AR0543_RAW_16BIT,{0x034E}, 0x02E0}, // Output Height
|
|
{AR0543_RAW_16BIT,{0x0344}, 0x0008}, // Column Start
|
|
{AR0543_RAW_16BIT,{0x0346}, 0x0008}, // Row Start
|
|
{AR0543_RAW_16BIT,{0x0348}, 0x0A25}, // Column End
|
|
{AR0543_RAW_16BIT,{0x034A}, 0x05C5}, // Row End
|
|
#ifdef CONFIG_ME175CG
|
|
{AR0543_RAW_16BIT,{0x3040}, 0xC4C3}, //Read Mode
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3040}, 0x04C3}, //Read Mode
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3010}, 0x0184}, // Fine Correction
|
|
{AR0543_RAW_16BIT,{0x3012}, 0x04A0}, // Coarse Integration Time
|
|
{AR0543_RAW_16BIT,{0x3014}, 0x05F8}, // Fine Integration Time
|
|
{AR0543_RAW_16BIT,{0x0340}, 0x04A1}, // Frame Lines
|
|
{AR0543_RAW_16BIT,{0x0342}, 0x0C4E}, // Line Length
|
|
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x00}, // GROUPED_PARAMETER_HOLD
|
|
{AR0543_RAW_TOK_DELAY, {0}, 5},//DELAY=5
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
|
|
static struct ar0543_raw_reg const ar0543_raw_VGA_30fps[] = {
|
|
//[656*496 @30FPS] }, // 668*500 that bining from 2592*1944 and scale from 1296*972
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x01}, // GROUPED_PARAMETER_HOLD = 0x1
|
|
|
|
// Timing Settings
|
|
{AR0543_RAW_16BIT,{0x0400}, 0x0002}, // scaling_mode
|
|
{AR0543_RAW_16BIT,{0x0404}, 0x001F}, // scale_m
|
|
{AR0543_RAW_16BIT,{0x034C}, 0x029C}, // Output Width
|
|
{AR0543_RAW_16BIT,{0x034E}, 0x01F4}, // Output Height
|
|
{AR0543_RAW_16BIT,{0x0344}, 0x0008}, // Column Start
|
|
{AR0543_RAW_16BIT,{0x0346}, 0x0008}, // Row Start
|
|
{AR0543_RAW_16BIT,{0x0348}, 0x0A25}, // Column End
|
|
{AR0543_RAW_16BIT,{0x034A}, 0x079D}, // Row End
|
|
#ifdef CONFIG_ME175CG
|
|
{AR0543_RAW_16BIT,{0x3040}, 0xC4C3}, //Read Mode
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3040}, 0x04C3}, //Read Mode
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3010}, 0x0184}, // Fine Correction
|
|
{AR0543_RAW_16BIT,{0x3012}, 0x0414}, // Coarse Integration Time
|
|
{AR0543_RAW_16BIT,{0x3014}, 0x05F8}, // Fine Integration Time
|
|
{AR0543_RAW_16BIT,{0x0340}, 0x0415}, // Frame Lines
|
|
{AR0543_RAW_16BIT,{0x0342}, 0x0DF4}, // Line Length
|
|
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x00}, // GROUPED_PARAMETER_HOLD
|
|
{AR0543_RAW_TOK_DELAY, {0}, 5},//DELAY=5
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static struct ar0543_raw_reg const ar0543_raw_CIF_30fps[] = {
|
|
//[368*304 @30FPS]}, // 432*324 that bining from 2592*1944 and scale from 1296*972
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x01}, // GROUPED_PARAMETER_HOLD = 0x1
|
|
|
|
// Timing Settings
|
|
{AR0543_RAW_16BIT,{0x0400}, 0x0002}, // scaling_mode
|
|
{AR0543_RAW_16BIT,{0x0404}, 0x0030}, // scale_m
|
|
{AR0543_RAW_16BIT,{0x034C}, 0x01B0}, // Output Width
|
|
{AR0543_RAW_16BIT,{0x034E}, 0x0144}, // Output Height
|
|
{AR0543_RAW_16BIT,{0x0344}, 0x0008}, // Column Start
|
|
{AR0543_RAW_16BIT,{0x0346}, 0x0008}, // Row Start
|
|
{AR0543_RAW_16BIT,{0x0348}, 0x0A25}, // Column End
|
|
{AR0543_RAW_16BIT,{0x034A}, 0x079D}, // Row End
|
|
#ifdef CONFIG_ME175CG
|
|
{AR0543_RAW_16BIT,{0x3040}, 0xC4C3}, //Read Mode
|
|
#else
|
|
{AR0543_RAW_16BIT,{0x3040}, 0x04C3}, //Read Mode
|
|
#endif
|
|
{AR0543_RAW_16BIT,{0x3010}, 0x0184}, // Fine Correction
|
|
{AR0543_RAW_16BIT,{0x3012}, 0x0414}, // Coarse Integration Time
|
|
{AR0543_RAW_16BIT,{0x3014}, 0x05F8}, // Fine Integration Time
|
|
{AR0543_RAW_16BIT,{0x0340}, 0x0415}, // Frame Lines
|
|
{AR0543_RAW_16BIT,{0x0342}, 0x0DF4}, // Line Length
|
|
|
|
{AR0543_RAW_8BIT,{0x0104}, 0x00}, // GROUPED_PARAMETER_HOLD
|
|
{AR0543_RAW_TOK_DELAY, {0}, 5},//DELAY=5
|
|
{AR0543_RAW_TOK_TERM, {0}, 0}
|
|
};
|
|
|
|
static struct ar0543_raw_resolution ar0543_raw_res_preview[] = {
|
|
{
|
|
.desc = "PREVIEW_960p_30fps" ,
|
|
.width = 1296 ,
|
|
.height = 976 ,
|
|
.fps = 30 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0C4E, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x04F6, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_960p_30fps ,
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.skip_frames = 1, /*change skip num from 1 to 0 after 3A init
|
|
param invalid issue fixed*/
|
|
},
|
|
{
|
|
// For 2560x1920 output
|
|
.desc = "PREVIEW_2592x1944_15fps" ,
|
|
.width = 2592 ,
|
|
.height = 1944 ,
|
|
.fps = 15 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0E6E, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x07E5, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_2592x1944_15fps,
|
|
.bin_factor_x = 0,
|
|
.bin_factor_y = 0,
|
|
.skip_frames = 1,
|
|
},
|
|
};
|
|
|
|
#define N_RES_PREVIEW (ARRAY_SIZE(ar0543_raw_res_preview))
|
|
|
|
#if 0
|
|
static struct ar0543_raw_resolution ar0543_raw_res_still[] = {
|
|
{
|
|
// For 2560x1920 output
|
|
.desc = "STILL_2592x1944_15fps" ,
|
|
.width = 2592 ,
|
|
.height = 1944 ,
|
|
.fps = 15 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0E6E, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x07E5, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_2592x1944_15fps,
|
|
.bin_factor_x = 0,
|
|
.bin_factor_y = 0,
|
|
.skip_frames = 1,
|
|
},
|
|
};
|
|
|
|
#define N_RES_STILL (ARRAY_SIZE(ar0543_raw_res_still))
|
|
#endif
|
|
|
|
static struct ar0543_raw_resolution ar0543_raw_res_video[] = {
|
|
{
|
|
.desc = "VIDEO_CIF_30fps" ,
|
|
.width = 368 ,
|
|
.height = 304 ,
|
|
.fps = 30 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0DF4, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x0415, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_CIF_30fps ,
|
|
.bin_factor_x = 2,
|
|
.bin_factor_y = 2,
|
|
.skip_frames = 1,
|
|
},
|
|
{
|
|
.desc = "VIDEO_VGA_30fps" ,
|
|
.width = 656 ,
|
|
.height = 496 ,
|
|
.fps = 30 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0DF4, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x0415, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_VGA_30fps ,
|
|
.bin_factor_x = 2,
|
|
.bin_factor_y = 2,
|
|
.skip_frames = 1,
|
|
},
|
|
{
|
|
.desc = "VIDEO_720p_30fps" ,
|
|
.width = 1296 ,
|
|
.height = 736 ,
|
|
.fps = 30 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0C4E, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x04A1, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_720p_30fps ,
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.skip_frames = 1,
|
|
},
|
|
{
|
|
.desc = "VIDEO_960p_30fps" ,
|
|
.width = 1296 ,
|
|
.height = 976 ,
|
|
.fps = 30 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0C4E, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x04F6, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_960p_30fps ,
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.skip_frames = 1,
|
|
},
|
|
{
|
|
.desc = "VIDEO_1080p_30fps" ,
|
|
.width = 1936 ,
|
|
.height = 1096 ,
|
|
.fps = 30 ,
|
|
.used = 0 ,
|
|
.pixels_per_line = 0x0BE0, /* consistent with regs arrays */
|
|
.lines_per_frame = 0x058F, /* consistent with regs arrays */
|
|
.regs = ar0543_raw_1080p_30fps ,
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.skip_frames = 1,
|
|
},
|
|
};
|
|
|
|
#define N_RES_VIDEO (ARRAY_SIZE(ar0543_raw_res_video))
|
|
|
|
static struct ar0543_raw_resolution *ar0543_raw_res = ar0543_raw_res_preview;
|
|
static int N_RES = N_RES_PREVIEW;
|
|
|
|
#endif
|