586 lines
16 KiB
C
586 lines
16 KiB
C
/*
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* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OV680_H__
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#define __OV680_H__
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#include <linux/atomisp_platform.h>
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#include <linux/atomisp.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <linux/v4l2-mediabus.h>
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#include <linux/types.h>
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#include <media/media-entity.h>
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#include <media/v4l2-chip-ident.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-subdev.h>
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#define OV680_NAME "ov680"
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#define OV680_CHIP_ID 0x680
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#define I2C_MSG_LENGTH 0x2
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#define REG_SC_BASE 0x6000
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#define REG_SCCB_SLAVE_BASE 0x6100
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#define REG_MIPI_RX1_BASE 0x6200
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#define REG_MIPI_RX0_BASE 0x6300
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#define REG_MIPI_RX3_BASE 0x6400
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#define REG_MIPI_RX2_BASE 0x6500
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#define REG_IMAGE_STITCH1_BASE 0x6600
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#define REG_IMAGE_STITCH2_BASE 0x6700
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#define REG_IMAGE_STITCH3_BASE 0x6800
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#define REG_MIPI_TX_BASE 0x6900
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#define REG_MIPI_BIST_BASE 0x6a00
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#define REG_SCCB_MASTER_BASE 0x6af0
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#define REG_MC_BASE 0x6b00
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#define REG_AVERAGE1_BASE 0x6c00
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#define REG_AVERAGE2_BASE 0x6c80
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#define REG_AEC1_BASE 0x6d00
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#define REG_AEC2_BASE 0x6d80
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#define REG_AEC1_PK_BASE 0x6e00
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#define REG_AWB1_PK_BASE 0x6f00
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#define REG_AWB2_PK_BASE 0x6f80
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#define REG_ISP_CONTRL_BASE 0x7000
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#define REG_LSC_BASE 0x7180
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#define REG_AWB1_BASE 0x7200
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#define REG_CONTRAST1_BASE 0x7280
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#define REG_DPC1_BASE 0x7300
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#define REG_DNS1_BASE 0x7380
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#define REG_CIP1_BASE 0x7400
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#define REG_CMX1_BASE 0x7480
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#define REG_GAMMA1_BASE 0x7500
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#define REG_UVDARK1_BASE 0x7580
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#define REG_SDE1_BASE 0x7600
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#define REG_SCALE1_BASE 0x7680
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#define REG_YUV_CROP1_BASE 0x7700
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#define REG_PRE_ISP_2_BASE 0x7800
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#define REG_LSC2_BASE 0x7880
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#define REG_AWB2_BASE 0x7900
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#define REG_CONSTRAST2_BASE 0x7980
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#define REG_DPC2_BASE 0x7a00
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#define REG_DNS2_BASE 0x7a80
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#define REG_CIP2_BASE 0x7b00
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#define REG_COLOR_MATRIX2_BASE 0x7b80
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#define REG_GAMMA2_BASE 0x7c00
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#define REG_UVDARK2_BASE 0x7c80
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#define REG_SDE2_BASE 0x7d00
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#define REG_SCALE2_BASE 0x7d80
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#define REG_YUV_CROP2_BASE 0x7e00
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#define REG_FIRWWARE_BASE 0x8000
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#define REG_SC_00 (REG_SC_BASE + 0x00)
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#define REG_SC_03 (REG_SC_BASE + 0x03)
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#define REG_SC_06 (REG_SC_BASE + 0x06)
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#define REG_SC_0A (REG_SC_BASE + 0x0a)
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#define REG_SC_66 (REG_SC_BASE + 0x66)
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#define REG_SC_90 (REG_SC_BASE + 0x90)
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#define REG_SC_93 (REG_SC_BASE + 0x93)
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#define REG_SC_03_GLOBAL_ENABLED 0x10
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#define REG_SC_03_GLOBAL_DISABLED 0x11
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#define REG_SC_66_GLOBAL_READY 0x18
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#define REG_SCCB_SLAVE_03 (REG_SCCB_SLAVE_BASE + 0x03)
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#define REG_MC_17 (REG_MC_BASE + 0x17)
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#define REG_MC_18 (REG_MC_BASE + 0x18)
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#define REG_MC_19 (REG_MC_BASE + 0x19)
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#define REG_MC_1A (REG_MC_BASE + 0x1a)
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#define REG_MC_1B (REG_MC_BASE + 0x1b)
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#define REG_MC_1C (REG_MC_BASE + 0x1c)
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#define REG_MC_1D (REG_MC_BASE + 0x1d)
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#define REG_YUV_CROP1_08 (REG_YUV_CROP1_BASE + 0x08)
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#define REG_YUV_CROP1_0B (REG_YUV_CROP1_BASE + 0x0b)
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/* detect input sensor */
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#define OV680_MAX_INPUT_SENSOR_NUM 2
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#define OV680_SENSOR_0_ID 0x20
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#define OV680_SENSOR_1_ID 0x6c
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#define OV680_SENSOR_REG0_VAL 0x97
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#define OV680_SENSOR_REG1_VAL 0x28
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/* ov680 command set definition */
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#define OV680_CMD_CIR_REG REG_MC_17 /* command interrupt register */
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#define OV680_CMD_OP_REG REG_MC_18 /* operation function */
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#define OV680_CMD_SUB_OP_REG REG_MC_19 /* sub function */
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#define OV680_CMD_PARAMETER_1 REG_MC_1A
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#define OV680_CMD_PARAMETER_2 REG_MC_1B
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#define OV680_CMD_PARAMETER_3 REG_MC_1C
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#define OV680_CMD_PARAMETER_4 REG_MC_1D
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#define OV680_CMD_CIR_IDLE_STATE 0x10
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#define OV680_CMD_CIR_OP_STATE 0x80
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#define OV680_CMD_CIR_SENSOR_ACCESS_STATE 0xf0
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#define OV680_CMD_SENSOR_CONFIG 0x81
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#define OV680_CMD_STREAM_CONFIG 0x82
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#define OV680_CMD_ISP_CONFIG 0x83
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#define OV680_CMD_READ_SENSOR 0x84
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#define OV680_CMD_WRITE_SENSOR 0x85
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#define OV680_CONFIG_SENSOR_720p 0x00
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#define OV680_CONFIG_SENSOR_VGA 0x01
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#define OV680_CONFIG_SENSOR_15FPS 0x11
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#define OV680_CONFIG_SENSOR_30FPS 0x13
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#define OV680_CONFIG_SENSOR_60FPS 0x15
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/* stream config sub function */
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#define OV680_CONFIG_STREAM_DEFAULT 0x01
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#define OV680_CONFIG_STREAM_S0_S0_A 0x00
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#define OV680_CONFIG_STREAM_S1_S1_A 0x11
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#define OV680_CONFIG_STREAM_S0_S1_A 0x01
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#define OV680_CONFIG_STREAM_S1_S0_A 0x10
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/* for 0x6b1b - virtual channel*/
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#define OV680_CONFIG_STREAM_INDEX_VC0 0x00
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#define OV680_CONFIG_STREAM_INDEX_VC1 0x55
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#define OV680_CONFIG_STREAM_INDEX_VC2 0xAA
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#define OV680_CONFIG_STREAM_INDEX_VC3 0xFF
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/* for 0x6b1c - index output group*/
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#define OV680_CONFIG_STREAM_INDEX_GROUP_1_SENSOR 0x01 /* 1280 x 720 */
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#define OV680_CONFIG_STREAM_INDEX_GROUP_2_SENSOR 0x02 /* 2560 x 720 */
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#define OV680_CONFIG_STREAM_INDEX_GROUP_NA_1 0x03
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#define OV680_CONFIG_STREAM_INDEX_GROUP_NA_2 0x04
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/* for 0x6b1d - index output group*/
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#define OV680_CONFIG_STREAM_INDEX_GROUP_720P 0x00 /* 1280 x 720 */
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#define OV680_CONFIG_STREAM_INDEX_GROUP_VGA 0x01 /* 640 x 480 */
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/* config isp */
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#define OV680_CONFIG_ISP_AEC_AGC_ON 0x00
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#define OV680_CONFIG_ISP_AEC_AGC_OFF 0x01
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#define OV680_CONFIG_ISP_AEC_TARGET_SET 0x02
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#define OV680_CONFIG_ISP_AEC_WEIGHT_SET 0x03
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#define OV680_CONFIG_ISP_DPC_ON 0x00
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#define OV680_CONFIG_ISP_DPC_OFF 0x01
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#define OV680_CONFIG_ISP_ISP_ON 0x02
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#define OV680_CONFIG_ISP_ISP_OFF 0x03
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#define OV680_CONFIG_ISP_LENC_ON 0x02
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#define OV680_CONFIG_ISP_LENS_OFF 0x03
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/* Todo: to define more ov680 register names */
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#define OV680_FIRMWARE_SIZE (33020) /* size =0xb610 - 0x8000 */
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#define OV680_MAX_RATIO_MISMATCH 10 /* Unit in percentage */
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enum ov680_tok_type {
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OV680_8BIT = 0x0001,
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OV680_16BIT = 0x0002,
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OV680_TOK_TERM = 0xf000, /* terminating token for reg list */
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OV680_TOK_DELAY = 0xfe00 /* delay token for reg list */
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};
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#define OV680_TOK_MASK 0xfff0
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/**
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* struct ov680_reg - 680 sensor register format
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* @reg: 16-bit offset to register
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* @val: 8-bit register value
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*/
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struct ov680_reg {
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enum ov680_tok_type type;
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u16 reg;
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u8 val;
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};
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#define OV680_MAX_WRITE_BUF_SIZE 32
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struct ov680_write_buffer {
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u16 addr;
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u8 data[OV680_MAX_WRITE_BUF_SIZE];
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};
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struct ov680_write_ctrl {
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int index;
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struct ov680_write_buffer buffer;
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};
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enum ov680_contexts {
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CONTEXT_PREVIEW = 0,
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CONTEXT_SNAPSHOT,
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CONTEXT_VIDEO,
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CONTEXT_NUM
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};
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struct ov680_res_struct {
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u16 width;
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u16 height;
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u16 fps;
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};
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struct ov680_firmware {
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u32 cmd_count; /* The total count of commands stored in FW */
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u32 cmd_size; /* The size of each command's storing space */
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};
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struct ov680_device {
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struct v4l2_subdev sd;
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struct media_pad pad;
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struct mutex input_lock; /* Serialize access to the device settings */
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struct v4l2_mbus_framefmt format;
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struct camera_sensor_platform_data *platform_data;
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int fw_index;
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int streaming;
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unsigned int num_lanes;
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int bayer_fmt;
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enum v4l2_mbus_pixelcode mbus_pixelcode;
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bool sys_activated;
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bool power_on;
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bool probed;
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struct v4l2_ctrl_handler ctrl_handler;
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struct v4l2_ctrl *run_mode;
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enum ov680_contexts cur_context;
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const struct firmware *fw;
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const struct ov680_reg *ov680_fw;
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};
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static struct ov680_res_struct ov680_res_list[] = {
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{
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.width = 1280,
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.height = 1440,
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.fps = 30,
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},
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};
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#define N_FW (ARRAY_SIZE(ov680_res_list))
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/* ov680 init clock pll instructions */
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static struct ov680_reg const ov680_init_clock_pll[] = {
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/*
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*----Start OV680 Clock and PLL configuration-----
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*new setting for 19.2M---------------------------
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*CCLK (sensor input clock/camera clock output)
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*/
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/* CCLK (camera clock) divider, 19.2/2=9.6MHz */
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{OV680_8BIT, 0x601a, 0x02},
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/* Common initial setting */
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/* Reset MC to disable looking for F/W from E2PROM */
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{OV680_8BIT, 0x6b00, 0x10},
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/* MIPI Rx CIF sel Rx0 PHY clk (MIPI receiver sync clock select */
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{OV680_8BIT, 0x6001, 0xa8},
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/* Clock Drive Strength --YM (CMD_RDY driver - open drain) */
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{OV680_8BIT, 0x6060, 0x3C},
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/* PLL1 - for system clock */
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{OV680_8BIT, 0x6020, 0x64},
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{OV680_8BIT, 0x6021, 0x22},
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{OV680_8BIT, 0x6022, 0x15},
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{OV680_8BIT, 0x6023, 0x12},
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{OV680_8BIT, 0x6024, 0x90},
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/* sys clk = pll_sysclk/2 = 46.4 MHz */
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{OV680_8BIT, 0x6018, 0x02},
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/* PLL2 - for MIPI */
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{OV680_8BIT, 0x6025, 0x59},
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{OV680_8BIT, 0x6026, 0x22},
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{OV680_8BIT, 0x6027, 0x15},
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{OV680_8BIT, 0x6028, 0x01},
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{OV680_8BIT, 0x6029, 0xa0},
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/* mipi_pclk = 96/2 = 48 */
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{OV680_8BIT, 0x6019, 0x02},
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/* 1000/mipi_clk */
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{OV680_8BIT, 0x6937, 0x11},
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/* Sel PLL2 sys_clk as Tx clk, PLL1 sys_clk as sys clk */
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{OV680_8BIT, 0x6103, 0x71},
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/* CCLK (sensor input clock) */
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/* Release AEC2&1, ISP2&1 */
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{OV680_8BIT, 0x6009, 0x00},
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/* Release Tx, stch 1~3, AWB1&2 */
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{OV680_8BIT, 0x600a, 0x00},
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/* Release Rx0~3 */
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{OV680_8BIT, 0x600b, 0x00},
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/* Release Tx, Rx PHY */
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{OV680_8BIT, 0x600c, 0x00},
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/* Enable CCLK, SCCB slave clock, MC, MC RAM */
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{OV680_8BIT, 0x6010, 0x3c},
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/* AEC2&1, ISP2&1 */
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{OV680_8BIT, 0x6011, 0xff},
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/* Sync FIFO, stch FIFO, Tx, stch 1~3, AWB1&2 */
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{OV680_8BIT, 0x6012, 0xff},
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/* Enable Rx0~Rx3 PHY clock */
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{OV680_8BIT, 0x6002, 0xff},
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{OV680_TOK_TERM, 0, 0}
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};
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/* ov680 pll change before fw loading */
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static struct ov680_reg const ov680_dw_fw_change_pll[] = {
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/*
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* OV680 Firmware download--Start
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* ----inlude OV680 and OV6710 setting in firmware-------------
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* change to pll clock
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*/
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/* Select PLL2 as system clock & MIPI transmitter clock source */
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{OV680_8BIT, 0x6103, 0x20},
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{OV680_8BIT, 0x6b00, 0x14},
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{OV680_8BIT, 0x6004, 0x00},
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{OV680_8BIT, 0x6008, 0x00},
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{OV680_8BIT, 0x6010, 0xff},
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{OV680_8BIT, 0x6101, 0x02},
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{OV680_8BIT, 0x6b0c, 0x00},
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{OV680_8BIT, 0x6b0d, 0x00},
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{OV680_TOK_TERM, 0, 0}
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};
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/* ov680 pll restore after fw loading */
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static struct ov680_reg const ov680_dw_fw_change_back_pll[] = {
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/* Change back PLL */
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{OV680_8BIT, 0x6103, 0x71},
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{OV680_8BIT, 0x6b56, 0x22},
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{OV680_8BIT, 0x6b57, 0xab},
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{OV680_8BIT, 0x6b00, 0x1c},
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{OV680_8BIT, 0x6b01, 0x04},
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{OV680_8BIT, 0x6b0e, 0xff},
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{OV680_TOK_TERM, 0, 0}
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};
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static struct ov680_reg const ov680_720p_2s_embedded_stream_on[] = {
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{OV680_8BIT, 0x6B18, 0x85},
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{OV680_8BIT, 0x6B19, 0x90},
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{OV680_8BIT, 0x6B1A, 0x01},
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{OV680_8BIT, 0x6B1B, 0x00},
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{OV680_8BIT, 0x6B1C, 0x01},
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{OV680_8BIT, 0x6B17, 0xF0},
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{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
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{OV680_8BIT, 0x6011, 0xFF}, /* AEC on */
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{OV680_TOK_TERM, 0, 0}
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};
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static struct ov680_reg const ov680_720p_2s_embedded_line[] = {
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/* Embedded Line Additional Setting 07/31/2014 */
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{OV680_8BIT, 0x6b18, 0x81}, /* TYPE_Sensor_Config */
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{OV680_8BIT, 0x6b19, 0x05}, /* 2560x720p SBS */
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{OV680_8BIT, 0x6b17, 0x80}, /* streaming */
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{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
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{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
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{OV680_8BIT, 0x6099, 0x00},
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{OV680_8BIT, 0x6914, 0x52},
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{OV680_8BIT, 0x6096, 0x11},
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{OV680_8BIT, 0x6b01, 0x24},
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{OV680_8BIT, 0x6b02, 0xc0},
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{OV680_8BIT, 0x6003, 0x10},
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{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
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{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
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{OV680_8BIT, 0x600a, 0x00},
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{OV680_TOK_TERM, 0, 0}
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};
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static struct ov680_reg const ov680_embedded_line_off[] = {
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/* @@ embedded line off */
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{OV680_8BIT, 0x6b18, 0x81}, /* TYPE_Sensor_Config */
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{OV680_8BIT, 0x6b19, 0x05}, /* 2560x720p SBS */
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{OV680_8BIT, 0x6b17, 0x80}, /* streaming */
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{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
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{OV680_8BIT, 0x6003, 0x11},
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{OV680_8BIT, 0x6b01, 0x04},
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{OV680_8BIT, 0x6b02, 0x00},
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{OV680_8BIT, 0x6b03, 0x00},
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{OV680_8BIT, 0x6096, 0x10},
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{OV680_8BIT, 0x6914, 0x00},
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{OV680_8BIT, 0x7002, 0x02},
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{OV680_8BIT, 0x7032, 0x02},
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{OV680_8BIT, 0x700c, 0x04},
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{OV680_8BIT, 0x700d, 0xff},
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{OV680_8BIT, 0x700e, 0x02},
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{OV680_8BIT, 0x700f, 0xcf},
|
|
|
|
{OV680_8BIT, 0x7704, 0x05},
|
|
{OV680_8BIT, 0x7705, 0x00},
|
|
{OV680_8BIT, 0x7706, 0x02},
|
|
{OV680_8BIT, 0x7707, 0xd0},
|
|
|
|
{OV680_8BIT, 0x703c, 0x04},
|
|
{OV680_8BIT, 0x703d, 0xff},
|
|
{OV680_8BIT, 0x703e, 0x02},
|
|
{OV680_8BIT, 0x703f, 0xcf},
|
|
|
|
{OV680_8BIT, 0x7800, 0x00},
|
|
{OV680_8BIT, 0x7801, 0x01},
|
|
{OV680_8BIT, 0x7811, 0x30},
|
|
|
|
{OV680_8BIT, 0x7e04, 0x05},
|
|
{OV680_8BIT, 0x7e05, 0x00},
|
|
{OV680_8BIT, 0x7e06, 0x02},
|
|
{OV680_8BIT, 0x7e07, 0xd0},
|
|
|
|
{OV680_8BIT, 0x7002, 0x02},
|
|
{OV680_8BIT, 0x7032, 0x02},
|
|
|
|
{OV680_8BIT, 0x608c, 0x05},
|
|
{OV680_8BIT, 0x608d, 0x00},
|
|
{OV680_8BIT, 0x608e, 0x05},
|
|
{OV680_8BIT, 0x608f, 0xa0},
|
|
{OV680_8BIT, 0x6090, 0x05},
|
|
{OV680_8BIT, 0x6091, 0x00},
|
|
{OV680_8BIT, 0x6092, 0x02},
|
|
{OV680_8BIT, 0x6093, 0xd0},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x20},
|
|
{OV680_8BIT, 0x6AF2, 0x01},
|
|
{OV680_8BIT, 0x6AF3, 0x00},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x20},
|
|
{OV680_8BIT, 0x6AF2, 0x43},
|
|
{OV680_8BIT, 0x6AF3, 0x07},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x20},
|
|
{OV680_8BIT, 0x6AF2, 0x01},
|
|
{OV680_8BIT, 0x6AF3, 0x00},
|
|
{OV680_8BIT, 0x6AF5, 0x01},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x6c},
|
|
{OV680_8BIT, 0x6AF2, 0x01},
|
|
{OV680_8BIT, 0x6AF3, 0x00},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x6c},
|
|
{OV680_8BIT, 0x6AF2, 0x43},
|
|
{OV680_8BIT, 0x6AF3, 0x07},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x6c},
|
|
{OV680_8BIT, 0x6AF2, 0x01},
|
|
{OV680_8BIT, 0x6AF3, 0x00},
|
|
{OV680_8BIT, 0x6AF5, 0x01},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6880, 0x01},
|
|
{OV680_8BIT, 0x6881, 0x60},
|
|
{OV680_8BIT, 0x6840, 0x01},
|
|
{OV680_8BIT, 0x6841, 0x60},
|
|
|
|
{OV680_8BIT, 0x6b02, 0x0c},
|
|
{OV680_8BIT, 0x6b03, 0x00},
|
|
|
|
/*
|
|
* sensor system change clock -48M to match OV8858 clock support
|
|
* for HW sync
|
|
*/
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x01},
|
|
{OV680_8BIT, 0x6AF3, 0x00},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x30},
|
|
{OV680_8BIT, 0x6AF3, 0x02},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x38},
|
|
{OV680_8BIT, 0x6AF3, 0x23},
|
|
{OV680_8BIT, 0x6AF5, 0x30},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x38},
|
|
{OV680_8BIT, 0x6AF3, 0x26},
|
|
{OV680_8BIT, 0x6AF5, 0x05},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x38},
|
|
{OV680_8BIT, 0x6AF3, 0x27},
|
|
{OV680_8BIT, 0x6AF5, 0xfd},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x43},
|
|
{OV680_8BIT, 0x6AF3, 0x0d},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x43},
|
|
{OV680_8BIT, 0x6AF3, 0x0e},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x43},
|
|
{OV680_8BIT, 0x6AF3, 0x0f},
|
|
{OV680_8BIT, 0x6AF5, 0x00},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x4f},
|
|
{OV680_8BIT, 0x6AF3, 0x07},
|
|
{OV680_8BIT, 0x6AF5, 0x23},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x4f},
|
|
{OV680_8BIT, 0x6AF3, 0x0f},
|
|
{OV680_8BIT, 0x6AF5, 0xa2},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
{OV680_TOK_DELAY, 0x0, 0xC6}, /* sleep 198ms */
|
|
|
|
/* sensor wake up */
|
|
{OV680_8BIT, 0x6AF1, 0x90},
|
|
{OV680_8BIT, 0x6AF2, 0x01},
|
|
{OV680_8BIT, 0x6AF3, 0x00},
|
|
{OV680_8BIT, 0x6AF5, 0x01},
|
|
{OV680_8BIT, 0x6AF9, 0x37},
|
|
|
|
/* Turn on AEC/AGC */
|
|
{OV680_8BIT, 0x6B48, 0x00},
|
|
{OV680_8BIT, 0x6B19, 0x00},
|
|
{OV680_8BIT, 0x6B18, 0x83},
|
|
{OV680_8BIT, 0x6B17, 0x80},
|
|
|
|
{OV680_TOK_DELAY, 0x0, 0x64}, /* sleep 100ms */
|
|
|
|
{OV680_TOK_TERM, 0, 0}
|
|
};
|
|
|
|
#endif
|