645 lines
18 KiB
C
645 lines
18 KiB
C
/*
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* Support for S5K6B2YX camera sensor.
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*
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* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*/
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#ifndef __S5K6B2YX_H__
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#define __S5K6B2YX_H__
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#include <linux/atomisp_platform.h>
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#include <linux/atomisp.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#include <linux/v4l2-mediabus.h>
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#include <media/media-entity.h>
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#include <media/v4l2-chip-ident.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-subdev.h>
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#include <media/v4l2-ctrls.h>
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#define S5K6B2YX_NAME "s5k6b2yx"
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#define V4L2_IDENT_S5K6B2YX 8245
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/* Defines for register writes and register array processing */
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#define S5K6B2YX_BYTE_MAX 30
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#define S5K6B2YX_SHORT_MAX 16
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#define I2C_MSG_LENGTH 0x2
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#define I2C_RETRY_COUNT 5
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#define S5K6B2YX_TEST_PATTERN_MODE 0x0601
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#define S5K6B2YX_HFLIP_BIT 0x1
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#define S5K6B2YX_VFLIP_BIT 0x2
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#define S5K6B2YX_VFLIP_OFFSET 1
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#define S5K6B2YX_IMG_ORIENTATION 0x0101
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#define I2C_RETRY_COUNT 5
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#define MAX_FMTS 1
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#define S5K6B2YX_PID_LOW 0x1
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#define S5K6B2YX_PID_HIGH 0x0
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#define S5K6B2YX_REV 0x1
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#define S5K6B2YX_MOD_ID 0x6B20
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#define S5K6B2YX_RES_WIDTH_MAX 1936
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#define S5K6B2YX_RES_HEIGHT_MAX 1096
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#define S5K6B2YX_FINE_INTEGRATION_TIME 0x0200
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#define S5K6B2YX_COARSE_INTEGRATION_TIME 0x0202
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#define S5K6B2YX_GLOBAL_GAIN 0x0204
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#define S5K6B2YX_FINE_INTG_TIME_MIN 0
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#define S5K6B2YX_FINE_INTG_TIME_MAX_MARGIN 0
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#define S5K6B2YX_COARSE_INTEGRATION_TIME_MARGIN 6
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#define S5K6B2YX_COARSE_INTEGRATION_TIME_MIN 1
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#define S5K6B2YX_MAX_EXPOSURE_SUPPORTED (0xffff - S5K6B2YX_COARSE_INTEGRATION_TIME_MARGIN)
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#define S5K6B2YX_MAX_GLOBAL_GAIN_SUPPORTED 0x0200
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#define S5K6B2YX_MIN_GLOBAL_GAIN_SUPPORTED 0x0020
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#define S5K6B2YX_INTG_BUF_COUNT 2
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#define S5K6B2YX_VT_PIX_CLK_DIV 0x0300
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#define S5K6B2YX_VT_SYS_CLK_DIV 0x0302
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#define S5K6B2YX_PRE_PLL_CLK_DIV 0x0304
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#define S5K6B2YX_PLL_MULTIPLIER 0x0306
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#define S5K6B2YX_FRAME_LENGTH_LINES 0x0340
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#define S5K6B2YX_MCLK 192
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#define S5K6B2YX_HORIZONTAL_START_H 0x0344
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#define S5K6B2YX_VERTICAL_START_H 0x0346
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#define S5K6B2YX_HORIZONTAL_END_H 0x0348
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#define S5K6B2YX_VERTICAL_END_H 0x034a
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#define S5K6B2YX_HORIZONTAL_OUTPUT_SIZE_H 0x034c
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#define S5K6B2YX_VERTICAL_OUTPUT_SIZE_H 0x034e
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/*
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* focal length bits definition:
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* bits 31-16: numerator, bits 15-0: denominator
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*/
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#define S5K6B2YX_FOCAL_LENGTH_DEFAULT 0x14a0064
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/*
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* current f-number bits definition:
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* bits 31-16: numerator, bits 15-0: denominator
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*/
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#define S5K6B2YX_F_NUMBER_DEFAULT 0x18000a
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/*
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* f-number range bits definition:
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* bits 31-24: max f-number numerator
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* bits 23-16: max f-number denominator
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* bits 15-8: min f-number numerator
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* bits 7-0: min f-number denominator
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*/
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#define S5K6B2YX_F_NUMBER_RANGE 0x180a180a
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#define S5K6B2YX_BIN_FACTOR_MAX 2
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/* Defines for lens/VCM */
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#define S5K6B2YX_FOCAL_LENGTH_NUM 185 /* 1.85 mm */
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#define S5K6B2YX_FOCAL_LENGTH_DEM 100
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#define S5K6B2YX_F_NUMBER_DEFAULT_NUM 24 /* F/2.4 */
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#define S5K6B2YX_F_NUMBER_DEM 10
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#define S5K6B2YX_INVALID_CONFIG 0xffffffff
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#define v4l2_format_capture_type_entry(_width, _height, \
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_pixelformat, _bytesperline, _colorspace) \
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{\
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.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,\
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.fmt.pix.width = (_width),\
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.fmt.pix.height = (_height),\
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.fmt.pix.pixelformat = (_pixelformat),\
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.fmt.pix.bytesperline = (_bytesperline),\
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.fmt.pix.colorspace = (_colorspace),\
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.fmt.pix.sizeimage = (_height)*(_bytesperline),\
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}
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#define s_output_format_entry(_width, _height, _pixelformat, \
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_bytesperline, _colorspace, _fps) \
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{\
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.v4l2_fmt = v4l2_format_capture_type_entry(_width, \
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_height, _pixelformat, _bytesperline, \
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_colorspace),\
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.fps = (_fps),\
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}
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#define s_output_format_reg_entry(_width, _height, _pixelformat, \
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_bytesperline, _colorspace, _fps, _reg_setting) \
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{\
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.s_fmt = s_output_format_entry(_width, _height,\
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_pixelformat, _bytesperline, \
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_colorspace, _fps),\
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.reg_setting = (_reg_setting),\
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}
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struct s_ctrl_id {
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struct v4l2_queryctrl qc;
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int (*s_ctrl)(struct v4l2_subdev *sd, u32 val);
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int (*g_ctrl)(struct v4l2_subdev *sd, u32 *val);
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};
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#define v4l2_queryctrl_entry_integer(_id, _name,\
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_minimum, _maximum, _step, \
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_default_value, _flags) \
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{\
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.id = (_id), \
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.type = V4L2_CTRL_TYPE_INTEGER, \
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.name = _name, \
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.minimum = (_minimum), \
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.maximum = (_maximum), \
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.step = (_step), \
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.default_value = (_default_value),\
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.flags = (_flags),\
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}
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#define v4l2_queryctrl_entry_boolean(_id, _name,\
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_default_value, _flags) \
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{\
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.id = (_id), \
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.type = V4L2_CTRL_TYPE_BOOLEAN, \
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.name = _name, \
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.minimum = 0, \
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.maximum = 1, \
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.step = 1, \
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.default_value = (_default_value),\
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.flags = (_flags),\
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}
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#define s_ctrl_id_entry_integer(_id, _name, \
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_minimum, _maximum, _step, \
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_default_value, _flags, \
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_s_ctrl, _g_ctrl) \
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{\
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.qc = v4l2_queryctrl_entry_integer(_id, _name,\
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_minimum, _maximum, _step,\
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_default_value, _flags), \
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.s_ctrl = _s_ctrl, \
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.g_ctrl = _g_ctrl, \
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}
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#define s_ctrl_id_entry_boolean(_id, _name, \
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_default_value, _flags, \
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_s_ctrl, _g_ctrl) \
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{\
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.qc = v4l2_queryctrl_entry_boolean(_id, _name,\
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_default_value, _flags), \
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.s_ctrl = _s_ctrl, \
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.g_ctrl = _g_ctrl, \
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}
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enum s5k6b2yx_tok_type {
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S5K6B2YX_8BIT = 0x0001,
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S5K6B2YX_16BIT = 0x0002,
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S5K6B2YX_RMW = 0x0010,
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S5K6B2YX_TOK_TERM = 0xf000, /* terminating token for reg list */
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S5K6B2YX_TOK_DELAY = 0xfe00, /* delay token for reg list */
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S5K6B2YX_TOK_MASK = 0xfff0
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};
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enum s5k6b2yx_mode {
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CAM_HW_STBY = 0, /* hw standby mode */
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CAM_SW_STBY, /* sw standby mode */
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CAM_VIS_STBY /* low power vision sening standby mode */
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};
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/*
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* If register address or register width is not 32 bit width,
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* user needs to convert it manually
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*/
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struct s_register_setting {
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u32 reg;
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u32 val;
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};
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struct s_output_format {
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struct v4l2_format v4l2_fmt;
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int fps;
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};
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struct s5k6b2yx_device {
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struct v4l2_subdev sd;
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struct media_pad pad;
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struct v4l2_mbus_framefmt format;
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struct camera_sensor_platform_data *platform_data;
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struct mutex input_lock; /* serialize sensor's ioctl */
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struct s5k6b2yx_vcm *vcm_driver;
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int fmt_idx;
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int status;
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int streaming;
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int power;
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int run_mode;
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int vt_pix_clk_freq_mhz;
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u16 sensor_id;
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u16 coarse_itg;
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u16 fine_itg;
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u16 gain;
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u16 digital_gain;
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u16 pixels_per_line;
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u16 lines_per_frame;
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u16 flip;
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u8 fps;
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u8 res;
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u8 type;
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u8 sensor_revision;
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enum s5k6b2yx_mode mode;
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struct v4l2_ctrl_handler ctrl_handler;
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struct v4l2_ctrl *link_freq;
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};
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/**
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* struct s5k6b2yx_reg - MI sensor register format
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* @type: type of the register
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* @reg: 16-bit offset to register
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* @val: 8/16/32-bit register value
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*
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* Define a structure for sensor register initialization values
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*/
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struct s5k6b2yx_reg {
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enum s5k6b2yx_tok_type type;
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u16 sreg;
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u32 val; /* @set value for read/mod/write, @mask */
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};
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#define to_s5k6b2yx_sensor(x) container_of(x, struct s5k6b2yx_device, sd)
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#define S5K6B2YX_MAX_WRITE_BUF_SIZE 30
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struct s5k6b2yx_write_buffer {
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u16 addr;
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u8 data[S5K6B2YX_MAX_WRITE_BUF_SIZE];
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};
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struct s5k6b2yx_write_ctrl {
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int index;
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struct s5k6b2yx_write_buffer buffer;
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};
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struct s5k6b2yx_format_struct {
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u8 *desc;
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struct regval_list *regs;
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u32 pixelformat;
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};
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struct s5k6b2yx_resolution {
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u8 *desc;
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const struct s5k6b2yx_reg *regs;
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int res;
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int width;
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int height;
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int fps;
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unsigned short pixels_per_line;
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unsigned short lines_per_frame;
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u8 bin_factor_x;
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u8 bin_factor_y;
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bool used;
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enum s5k6b2yx_mode mode;
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u32 skip_frames;
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u32 code;
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int mipi_freq;
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};
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struct s5k6b2yx_control {
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struct v4l2_queryctrl qc;
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int (*query)(struct v4l2_subdev *sd, s32 *value);
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int (*tweak)(struct v4l2_subdev *sd, int value);
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};
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/* init settings */
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static struct s5k6b2yx_reg const s5k6b2yx_init_config[] = {
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/* Vendor specific */
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{ S5K6B2YX_8BIT, 0x31d3, 0x01 }, /* efuse read en */
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{ S5K6B2YX_8BIT, 0x3426, 0x3a }, /* [4]corr_en[3:2]gain_b_sel,[1:0]gain_r_sel */
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{ S5K6B2YX_8BIT, 0x340d, 0x30 }, /* efuse clock off */
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{ S5K6B2YX_8BIT, 0x3067, 0x25 }, /* adc_sat[mV]=617mV */
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{ S5K6B2YX_8BIT, 0x307d, 0x08 }, /* dbr_tune_tgs */
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{ S5K6B2YX_8BIT, 0x307e, 0x08 }, /* dbr_tune_rg */
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{ S5K6B2YX_8BIT, 0x307f, 0x08 }, /* dbr_tune_fdb */
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{ S5K6B2YX_8BIT, 0x3080, 0x04 }, /* dbr_tune_ntg */
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{ S5K6B2YX_8BIT, 0x3073, 0x73 }, /* comp1_bias, comp2_bias */
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{ S5K6B2YX_8BIT, 0x3074, 0x45 }, /* pix_bias, pix_bias_boost */
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{ S5K6B2YX_8BIT, 0x3075, 0xd4 }, /* clp_lvl */
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{ S5K6B2YX_8BIT, 0x3085, 0xf0 }, /* rdv_option; LOB_PLA enable */
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{ S5K6B2YX_8BIT, 0x3068, 0x55 }, /* ms[15:8]; x4~ */
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{ S5K6B2YX_8BIT, 0x3069, 0x00 }, /* ms[7:0]; x1~x4 */
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{ S5K6B2YX_8BIT, 0x3063, 0x08 }, /* cds_option[15:8];[11]ldb nmos sw enable=1 */
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{ S5K6B2YX_8BIT, 0x3064, 0x00 }, /* cds_option[7:0]; */
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{ S5K6B2YX_8BIT, 0x3010, 0x04 }, /* FD start 2->4 for low lux fluctuation */
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{ S5K6B2YX_8BIT, 0x3247, 0x11 }, /*[4] fadlc_blst_en */
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{ S5K6B2YX_8BIT, 0x3083, 0x00 }, /* blst_en_cintr = 16 */
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{ S5K6B2YX_8BIT, 0x3084, 0x10 },
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/* PLL Setting: ext_clk = 19.2MHz; PLL output = 744MHz */
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{ S5K6B2YX_8BIT, 0x0305, 0x04 }, /* pll_pre_pre_div = 4 */
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{ S5K6B2YX_8BIT, 0x0306, 0x00 },
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{ S5K6B2YX_8BIT, 0x0307, 0x9b }, /* pll_multiplier = 155 */
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/* Vendor specific */
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{ S5K6B2YX_8BIT, 0x3351, 0x02 },
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{ S5K6B2YX_8BIT, 0x3352, 0xdc },
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{ S5K6B2YX_8BIT, 0x3353, 0x00 },
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{ S5K6B2YX_8BIT, 0x3354, 0x00 },
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/* others */
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{ S5K6B2YX_8BIT, 0x7339, 0x03 }, /* [2]dphy_en1, [1]dphy_en0, [0] dhpy_en_clk */
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{ S5K6B2YX_8BIT, 0x0202, 0x03 },
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{ S5K6B2YX_8BIT, 0x0203, 0x88 }, /* TBD: Coarse_integration_time */
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{ S5K6B2YX_8BIT, 0x0204, 0x00 },
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{ S5K6B2YX_8BIT, 0x0205, 0x2a }, /* TBD: Analogue_gain_code_global */
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{S5K6B2YX_TOK_TERM, 0, 0}
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};
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/* Stream mode */
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static struct s5k6b2yx_reg const s5k6b2yx_suspend[] = {
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{S5K6B2YX_8BIT, 0x0100, 0x0 },
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{S5K6B2YX_TOK_TERM, 0, 0 },
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};
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static struct s5k6b2yx_reg const s5k6b2yx_streaming[] = {
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{S5K6B2YX_8BIT, 0x0100, 0x1 },
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{S5K6B2YX_TOK_TERM, 0, 0 },
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};
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static struct s5k6b2yx_reg const s5k6b2yx_vis_suspend[] = {
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{S5K6B2YX_8BIT, 0x4100, 0x0 },
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{S5K6B2YX_TOK_TERM, 0, 0 }
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};
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static struct s5k6b2yx_reg const s5k6b2yx_vis_streaming[] = {
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{S5K6B2YX_8BIT, 0x4100, 0x1 },
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{ S5K6B2YX_TOK_TERM, 0, 0}
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};
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/* GROUPED_PARAMETER_HOLD */
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static struct s5k6b2yx_reg const s5k6b2yx_param_hold[] = {
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{ S5K6B2YX_8BIT, 0x0104, 0x1 },
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{ S5K6B2YX_TOK_TERM, 0, 0 }
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};
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static struct s5k6b2yx_reg const s5k6b2yx_param_update[] = {
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{ S5K6B2YX_8BIT, 0x0104, 0x0 },
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{ S5K6B2YX_TOK_TERM, 0, 0 }
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};
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/* Settings */
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static struct s5k6b2yx_reg const s5k6b2yx_184x104_15fps[] = {
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{ S5K6B2YX_8BIT, 0x4307, 0xB7}, /* pll_multiplier */
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{ S5K6B2YX_8BIT, 0x6030, 0x13}, /* EXTCLK_MHz */
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{ S5K6B2YX_8BIT, 0x6031, 0x37},
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{ S5K6B2YX_8BIT, 0x3412, 0x4B}, /* streaming_enable_time */
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{ S5K6B2YX_8BIT, 0x3413, 0x13},
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{ S5K6B2YX_8BIT, 0x7412, 0x07}, /* streaming_enable_time_alv */
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{ S5K6B2YX_8BIT, 0x7413, 0x80},
|
|
|
|
/* 8bit mode */
|
|
{ S5K6B2YX_8BIT, 0x7030, 0x0E},
|
|
{ S5K6B2YX_8BIT, 0x7031, 0x2F},
|
|
|
|
/* Analog Tuning */
|
|
{ S5K6B2YX_8BIT, 0x7067, 0x00}, /* adc_sat_alv (392mV) (20120807) */
|
|
{ S5K6B2YX_8BIT, 0x7074, 0x22}, /* pix_bias_alv, pix_bias_boost_alv */
|
|
|
|
|
|
/* Dark Tuning */
|
|
{ S5K6B2YX_8BIT, 0x7402, 0x1F}, /* data_depedestal_adlc_alv */
|
|
{ S5K6B2YX_8BIT, 0x7403, 0xC0},
|
|
{ S5K6B2YX_8BIT, 0x7247, 0x01}, /* adlc_option (20121116) */
|
|
|
|
/* Remove Dark Band (20121031) */
|
|
{ S5K6B2YX_8BIT, 0x7412, 0x09}, /* streaming_enable_time_alv (103.9usec) */
|
|
{ S5K6B2YX_8BIT, 0x7413, 0xB9},
|
|
{ S5K6B2YX_8BIT, 0x7430, 0x05}, /* cintc_default_1_alv */
|
|
{ S5K6B2YX_8BIT, 0x7432, 0x02}, /* cintc_default_2_alv */
|
|
{ S5K6B2YX_8BIT, 0x7433, 0x32},
|
|
|
|
/* Remove Sun spot (20120807) */
|
|
{ S5K6B2YX_8BIT, 0x7075, 0x3D}, /* clp_lvl_alv */
|
|
|
|
/* Remove CFPN (20120830) -> (20121026 EVT1) */
|
|
{ S5K6B2YX_8BIT, 0x7066, 0x09}, /* off_rst_alv */
|
|
|
|
|
|
/* AE setting (20121025 EVT1) */
|
|
/* weight */
|
|
{ S5K6B2YX_8BIT, 0x6000, 0x01},
|
|
{ S5K6B2YX_8BIT, 0x6001, 0x10},
|
|
{ S5K6B2YX_8BIT, 0x6002, 0x14},
|
|
{ S5K6B2YX_8BIT, 0x6003, 0x41},
|
|
{ S5K6B2YX_8BIT, 0x6004, 0x14},
|
|
{ S5K6B2YX_8BIT, 0x6005, 0x41},
|
|
{ S5K6B2YX_8BIT, 0x6006, 0x01},
|
|
{ S5K6B2YX_8BIT, 0x6007, 0x10},
|
|
|
|
/* number of pixel */
|
|
{ S5K6B2YX_8BIT, 0x5030, 0x1C},
|
|
{ S5K6B2YX_8BIT, 0x5031, 0x08},
|
|
|
|
/* Speed */
|
|
{ S5K6B2YX_8BIT, 0x5034, 0x00},
|
|
|
|
/* Innner Target Tolerance */
|
|
{ S5K6B2YX_8BIT, 0x503F, 0x03},
|
|
|
|
/* patch height (20121116) */
|
|
{ S5K6B2YX_8BIT, 0x6015, 0x19},
|
|
|
|
/* G + R Setting (20120813) */
|
|
/* Vision Senser Data = 0.5*Gr + 0.5*R */
|
|
{ S5K6B2YX_8BIT, 0x6029, 0x02}, /* [2:0] : 1bit integer, 2bit fraction */
|
|
{ S5K6B2YX_8BIT, 0x602A, 0x02}, /* [2:0] : 1bit integer, 2bit fraction */
|
|
|
|
|
|
/* For Analog Gain 16x (20120904) */
|
|
{ S5K6B2YX_8BIT, 0x7018, 0xCF},
|
|
{ S5K6B2YX_8BIT, 0x7019, 0xDB},
|
|
{ S5K6B2YX_8BIT, 0x702A, 0x8D},
|
|
{ S5K6B2YX_8BIT, 0x702B, 0x60},
|
|
{ S5K6B2YX_8BIT, 0x5035, 0x02}, /* analog gain max */
|
|
|
|
|
|
/* BIT_RATE_MBPS_alv (585Mbps) */
|
|
{ S5K6B2YX_8BIT, 0x7351, 0x02},
|
|
{ S5K6B2YX_8BIT, 0x7352, 0x49},
|
|
{ S5K6B2YX_8BIT, 0x7353, 0x00},
|
|
{ S5K6B2YX_8BIT, 0x7354, 0x00},
|
|
|
|
{ S5K6B2YX_8BIT, 0x7339, 0x03}, /* [2]dphy_en1, [1]dphy_en0, [0] dhpy_en_clk */
|
|
#ifdef VISION_MODE_TEST_PATTERN
|
|
{ S5K6B2YX_8BIT, 0x7203, 0x42}, /* to enable test pattern */
|
|
#endif
|
|
|
|
{ S5K6B2YX_TOK_TERM, 0, 0 }
|
|
};
|
|
|
|
static struct s5k6b2yx_reg const s5k6b2yx_1936x1096_30fps[] = {
|
|
/* Vendor specific */
|
|
{ S5K6B2YX_8BIT, 0x31d3, 0x01 }, /* efuse read en */
|
|
{ S5K6B2YX_8BIT, 0x3426, 0x3a }, /* [4]corr_en[3:2]gain_b_sel,[1:0]gain_r_sel */
|
|
{ S5K6B2YX_8BIT, 0x340d, 0x30 }, /* efuse clock off */
|
|
|
|
{ S5K6B2YX_8BIT, 0x3067, 0x25 }, /* adc_sat[mV]=617mV */
|
|
{ S5K6B2YX_8BIT, 0x307d, 0x08 }, /* dbr_tune_tgs */
|
|
{ S5K6B2YX_8BIT, 0x307e, 0x08 }, /* dbr_tune_rg */
|
|
{ S5K6B2YX_8BIT, 0x307f, 0x08 }, /* dbr_tune_fdb */
|
|
{ S5K6B2YX_8BIT, 0x3080, 0x04 }, /* dbr_tune_ntg */
|
|
{ S5K6B2YX_8BIT, 0x3073, 0x73 }, /* comp1_bias, comp2_bias */
|
|
{ S5K6B2YX_8BIT, 0x3074, 0x45 }, /* pix_bias, pix_bias_boost */
|
|
{ S5K6B2YX_8BIT, 0x3075, 0xd4 }, /* clp_lvl */
|
|
{ S5K6B2YX_8BIT, 0x3085, 0xf0 }, /* rdv_option; LOB_PLA enable */
|
|
{ S5K6B2YX_8BIT, 0x3068, 0x55 }, /* ms[15:8]; x4~ */
|
|
{ S5K6B2YX_8BIT, 0x3069, 0x00 }, /* ms[7:0]; x1~x4 */
|
|
{ S5K6B2YX_8BIT, 0x3063, 0x08 }, /* cds_option[15:8];[11]ldb nmos sw enable=1 */
|
|
{ S5K6B2YX_8BIT, 0x3064, 0x00 }, /* cds_option[7:0]; */
|
|
{ S5K6B2YX_8BIT, 0x3010, 0x04 }, /* FD start 2->4 for low lux fluctuation */
|
|
|
|
{ S5K6B2YX_8BIT, 0x3247, 0x11 }, /*[4] fadlc_blst_en */
|
|
{ S5K6B2YX_8BIT, 0x3083, 0x00 }, /* blst_en_cintr = 16 */
|
|
{ S5K6B2YX_8BIT, 0x3084, 0x10 },
|
|
|
|
/* PLL Setting: ext_clk = 19.2MHz; PLL output = 744MHz */
|
|
{ S5K6B2YX_8BIT, 0x0305, 0x04 }, /* pll_pre_pre_div = 4 */
|
|
{ S5K6B2YX_8BIT, 0x0306, 0x00 },
|
|
{ S5K6B2YX_8BIT, 0x0307, 0x9b }, /* pll_multiplier = 155 */
|
|
|
|
/* Vendor specific */
|
|
{ S5K6B2YX_8BIT, 0x3351, 0x02 },
|
|
{ S5K6B2YX_8BIT, 0x3352, 0xdc },
|
|
{ S5K6B2YX_8BIT, 0x3353, 0x00 },
|
|
{ S5K6B2YX_8BIT, 0x3354, 0x00 },
|
|
|
|
/* others */
|
|
{ S5K6B2YX_8BIT, 0x7339, 0x03 }, /* [2]dphy_en1, [1]dphy_en0, [0] dhpy_en_clk */
|
|
{ S5K6B2YX_8BIT, 0x0202, 0x03 },
|
|
{ S5K6B2YX_8BIT, 0x0203, 0x88 }, /* TBD: Coarse_integration_time */
|
|
{ S5K6B2YX_8BIT, 0x0204, 0x00 },
|
|
{ S5K6B2YX_8BIT, 0x0205, 0x2a }, /* TBD: Analogue_gain_code_global */
|
|
|
|
/* Resolution Setting */
|
|
{ S5K6B2YX_8BIT, 0x0344, 0x00 }, /* x_addr_start MSB */
|
|
{ S5K6B2YX_8BIT, 0x0345, 0x00 }, /* x_addr_start LSB */
|
|
{ S5K6B2YX_8BIT, 0x0346, 0x00 }, /* y_addr_start MSB */
|
|
{ S5K6B2YX_8BIT, 0x0347, 0x00 }, /* y_addr_start LSB */
|
|
|
|
{ S5K6B2YX_8BIT, 0x0348, 0x07 }, /* x_addr_end MSB */
|
|
{ S5K6B2YX_8BIT, 0x0349, 0x8f }, /* x_addr_end LSB */
|
|
{ S5K6B2YX_8BIT, 0x034a, 0x04 }, /* y_addr_end MSB */
|
|
{ S5K6B2YX_8BIT, 0x034b, 0x47 }, /* y_addr_end LSB */
|
|
|
|
{ S5K6B2YX_8BIT, 0x034c, 0x07 }, /* x_output_size MSB */
|
|
{ S5K6B2YX_8BIT, 0x034d, 0x90 }, /* x_output_size LSB */
|
|
{ S5K6B2YX_8BIT, 0x034e, 0x04 }, /* y_output_size MSB */
|
|
{ S5K6B2YX_8BIT, 0x034f, 0x48 }, /* y_output_size LSB */
|
|
|
|
{ S5K6B2YX_8BIT, 0x0340, 0x04 }, /* frame_length_lines MSB */
|
|
{ S5K6B2YX_8BIT, 0x0341, 0x66 }, /* frame_length_lines LSB */
|
|
{ S5K6B2YX_8BIT, 0x0342, 0x08 }, /* line_length_pck MSB */
|
|
{ S5K6B2YX_8BIT, 0x0343, 0x9b }, /* line_length_pck LSB */
|
|
{ S5K6B2YX_TOK_TERM, 0, 0 }
|
|
};
|
|
|
|
struct s5k6b2yx_resolution s5k6b2yx_res_preview[] = {
|
|
{
|
|
.desc = "s5k6b2yx_184x104_15fps",
|
|
.regs = s5k6b2yx_184x104_15fps,
|
|
.width = 184,
|
|
.height = 104,
|
|
.fps = 15,
|
|
.pixels_per_line = 2203, /* consistent with regs arrays */
|
|
.lines_per_frame = 1126, /* consistent with regs arrays */
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.used = 0,
|
|
.skip_frames = 2,
|
|
.mipi_freq = 292000,
|
|
.code = V4L2_MBUS_FMT_SGRBG8_1X8,
|
|
.mode = CAM_VIS_STBY,
|
|
},
|
|
{
|
|
.desc = "s5k6b2yx_1936x1096_30fps",
|
|
.regs = s5k6b2yx_1936x1096_30fps,
|
|
.width = 1936,
|
|
.height = 1096,
|
|
.fps = 30,
|
|
.pixels_per_line = 2203, /* consistent with regs arrays */
|
|
.lines_per_frame = 1126, /* consistent with regs arrays */
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.used = 0,
|
|
.skip_frames = 2,
|
|
.mipi_freq = 372000,
|
|
.mode = CAM_SW_STBY,
|
|
.code = V4L2_MBUS_FMT_SGRBG10_1X10,
|
|
},
|
|
};
|
|
#define N_RES_PREVIEW (ARRAY_SIZE(s5k6b2yx_res_preview))
|
|
|
|
struct s5k6b2yx_resolution s5k6b2yx_res_still[] = {
|
|
{
|
|
.desc = "s5k6b2yx_1936x1096_30fps",
|
|
.regs = s5k6b2yx_1936x1096_30fps,
|
|
.width = 1936,
|
|
.height = 1096,
|
|
.fps = 30,
|
|
.pixels_per_line = 2203, /* consistent with regs arrays */
|
|
.lines_per_frame = 1126, /* consistent with regs arrays */
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.used = 0,
|
|
.skip_frames = 2,
|
|
.mipi_freq = 372000,
|
|
.mode = CAM_SW_STBY,
|
|
.code = V4L2_MBUS_FMT_SGRBG10_1X10,
|
|
},
|
|
};
|
|
#define N_RES_STILL (ARRAY_SIZE(s5k6b2yx_res_still))
|
|
|
|
struct s5k6b2yx_resolution s5k6b2yx_res_video[] = {
|
|
{
|
|
.desc = "s5k6b2yx_1936x1096_30fps",
|
|
.regs = s5k6b2yx_1936x1096_30fps,
|
|
.width = 1936,
|
|
.height = 1096,
|
|
.fps = 30,
|
|
.pixels_per_line = 2203, /* consistent with regs arrays */
|
|
.lines_per_frame = 1126, /* consistent with regs arrays */
|
|
.bin_factor_x = 1,
|
|
.bin_factor_y = 1,
|
|
.used = 0,
|
|
.skip_frames = 2,
|
|
.mipi_freq = 372000,
|
|
.mode = CAM_SW_STBY,
|
|
.code = V4L2_MBUS_FMT_SGRBG10_1X10,
|
|
},
|
|
};
|
|
#define N_RES_VIDEO (ARRAY_SIZE(s5k6b2yx_res_video))
|
|
|
|
struct s5k6b2yx_resolution *s5k6b2yx_res = s5k6b2yx_res_preview;
|
|
static int N_RES = N_RES_PREVIEW;
|
|
|
|
#endif
|