30680c6eb3
* Massdrop SAMD51 Massdrop SAMD51 keyboards initial project upload * Removing relocated files Removing files that were relocated and not deleted from previous location * LED queue fix and cleaning Cleaned some white space or comments. Fix for LED I2C command queue. Cleaned up interrupts. Added debug function for printing numbers to scope through m15 line. * Factory programmed serial usage Ability to use factory programmed serial in hub and keyboard usb descriptors * USB serial number and bugfix Added support for factory programmed serial and usage. Incorporated bootloader's conditional compiling to align project closer. Fixed issue when USB device attempted to send before enabled. General white space and comment cleanup. * Project cleanup Cleaned up project in terms of white space, commented code, and unecessary files. NKRO keyboard is now using correct setreport although KBD was fine to use. Fixed broken linkage to __xprintf for serial debug statements. * Fix for extra keys Fixed possible USB hang on extra keys report set missing * I2C cleanup I2C cleanup and file renames necessary for master branch merge * Boot tracing and clocks cleanup Added optional boot debug trace mode through debug LED codes. General clock code cleanup. * Relocate ARM/Atmel headers Moved ARM/Atmel header folder from drivers to lib and made necessary makefile changes. * Pull request changes Pull request changes * Keymap and compile flag fix Keymap fix for momentary layer. Potential compile flag fix for Travis CI failure. * va_list include fix Fix for va_list compile failure * Include file case fixes Fixes for include files with incorrect case * ctrl and alt67 keyboard readme Added ctrl and alt67 keyboard readme files
89 lines
4.8 KiB
C
89 lines
4.8 KiB
C
/**
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* \file
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*
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* \brief Instance description for DAC
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*
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* Copyright (c) 2017 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_DAC_INSTANCE_
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#define _SAMD51_DAC_INSTANCE_
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/* ========== Register definition for DAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_DAC_CTRLA (0x43002400) /**< \brief (DAC) Control A */
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#define REG_DAC_CTRLB (0x43002401) /**< \brief (DAC) Control B */
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#define REG_DAC_EVCTRL (0x43002402) /**< \brief (DAC) Event Control */
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#define REG_DAC_INTENCLR (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */
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#define REG_DAC_INTENSET (0x43002405) /**< \brief (DAC) Interrupt Enable Set */
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#define REG_DAC_INTFLAG (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */
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#define REG_DAC_STATUS (0x43002407) /**< \brief (DAC) Status */
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#define REG_DAC_SYNCBUSY (0x43002408) /**< \brief (DAC) Synchronization Busy */
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#define REG_DAC_DACCTRL0 (0x4300240C) /**< \brief (DAC) DAC 0 Control */
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#define REG_DAC_DACCTRL1 (0x4300240E) /**< \brief (DAC) DAC 1 Control */
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#define REG_DAC_DATA0 (0x43002410) /**< \brief (DAC) DAC 0 Data */
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#define REG_DAC_DATA1 (0x43002412) /**< \brief (DAC) DAC 1 Data */
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#define REG_DAC_DATABUF0 (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */
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#define REG_DAC_DATABUF1 (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */
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#define REG_DAC_DBGCTRL (0x43002418) /**< \brief (DAC) Debug Control */
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#define REG_DAC_RESULT0 (0x4300241C) /**< \brief (DAC) Filter Result 0 */
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#define REG_DAC_RESULT1 (0x4300241E) /**< \brief (DAC) Filter Result 1 */
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#else
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#define REG_DAC_CTRLA (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */
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#define REG_DAC_CTRLB (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */
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#define REG_DAC_EVCTRL (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */
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#define REG_DAC_INTENCLR (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */
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#define REG_DAC_INTENSET (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */
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#define REG_DAC_INTFLAG (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
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#define REG_DAC_STATUS (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */
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#define REG_DAC_SYNCBUSY (*(RoReg *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */
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#define REG_DAC_DACCTRL0 (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */
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#define REG_DAC_DACCTRL1 (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */
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#define REG_DAC_DATA0 (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */
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#define REG_DAC_DATA1 (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */
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#define REG_DAC_DATABUF0 (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */
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#define REG_DAC_DATABUF1 (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */
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#define REG_DAC_DBGCTRL (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */
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#define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
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#define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for DAC peripheral ========== */
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#define DAC_CHANNEL_SIZE 2 // Number of DACs
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#define DAC_DATA_SIZE 12 // Number of bits in data
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#define DAC_DMAC_ID_EMPTY_0 72
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#define DAC_DMAC_ID_EMPTY_1 73
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#define DAC_DMAC_ID_EMPTY_LSB 72
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#define DAC_DMAC_ID_EMPTY_MSB 73
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#define DAC_DMAC_ID_EMPTY_SIZE 2
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#define DAC_DMAC_ID_RESRDY_0 74
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#define DAC_DMAC_ID_RESRDY_1 75
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#define DAC_DMAC_ID_RESRDY_LSB 74
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#define DAC_DMAC_ID_RESRDY_MSB 75
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#define DAC_DMAC_ID_RESRDY_SIZE 2
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#define DAC_GCLK_ID 42 // Index of Generic Clock
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#define DAC_STEP 7 // Number of steps to reach full scale
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#endif /* _SAMD51_DAC_INSTANCE_ */
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