283 lines
6.8 KiB
C
283 lines
6.8 KiB
C
/*
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* PXA2xx SPI LPSS DMA support.
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*
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* Copyright (C) 2014, Intel Corporation
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* Author: Huiquan Zhong <huiquan.zhong@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/workqueue.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/pxa2xx_ssp.h>
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#include <linux/sizes.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/lpss_dma.h>
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#include "spi-pxa2xx.h"
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static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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bool error)
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{
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struct spi_message *msg = drv_data->cur_msg;
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/*
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* It is possible that one CPU is handling ROR interrupt and other
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* just gets DMA completion. Calling pump_transfers() twice for the
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* same transfer leads to problems thus we prevent concurrent calls
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* by using ->dma_running.
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*/
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if (atomic_dec_and_test(&drv_data->dma_running)) {
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void __iomem *reg = drv_data->ioaddr;
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/*
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* If the other CPU is still handling the ROR interrupt we
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* might not know about the error yet. So we re-check the
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* ROR bit here before we clear the status register.
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*/
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if (!error) {
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u32 status = read_SSSR(reg) & drv_data->mask_sr;
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error = status & SSSR_ROR;
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}
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/* Clear status & disable interrupts */
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write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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if (!error) {
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msg->actual_length += drv_data->len;
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msg->state = pxa2xx_spi_next_transfer(drv_data);
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} else {
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/* In case we got an error we disable the SSP now */
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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msg->state = ERROR_STATE;
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}
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tasklet_schedule(&drv_data->pump_transfers);
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}
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}
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static void pxa2xx_spi_dma_callback(void *data)
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{
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struct driver_data *drv_data = data;
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struct chip_data *chip = drv_data->cur_chip;
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void __iomem *reg = drv_data->ioaddr;
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u32 cr1;
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drv_data->tx += drv_data->tx_map_len;
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drv_data->rx += drv_data->rx_map_len;
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/* use interrupt to poll the last bytes */
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cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
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write_SSCR1(cr1, reg);
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}
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bool pxa2xx_spi_dma_is_possible(size_t len)
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{
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return len <= MAX_DMA_LEN;
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}
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int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
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{
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const struct chip_data *chip = drv_data->cur_chip;
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if (!chip->enable_dma)
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return 0;
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/* Don't bother with DMA if we can't do even a single burst */
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if (drv_data->len < chip->dma_burst_size)
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return 0;
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if (!drv_data->tx) {
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drv_data->tx = drv_data->dummy;
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drv_data->tx_end = drv_data->tx + drv_data->len;
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}
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if (!drv_data->rx) {
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drv_data->rx = drv_data->dummy;
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drv_data->rx_end = drv_data->rx + drv_data->len;
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}
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return 1;
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}
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irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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{
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void *lpss_dma = drv_data->dma_priv;
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u32 status;
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status = read_SSSR(drv_data->ioaddr) & drv_data->mask_sr;
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if (status & SSSR_ROR) {
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dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
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lpss_dma_stop_tx(lpss_dma);
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lpss_dma_stop_rx(lpss_dma);
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pxa2xx_spi_dma_transfer_complete(drv_data, true);
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return IRQ_HANDLED;
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}
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if (status & SSSR_TINT) {
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write_SSSR(SSSR_TINT, drv_data->ioaddr);
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if (drv_data->read(drv_data)) {
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pxa2xx_spi_dma_transfer_complete(drv_data, false);
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return IRQ_HANDLED;
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}
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}
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/* Drain rx fifo, Fill tx fifo and prevent overruns */
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do {
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if (drv_data->read(drv_data)) {
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pxa2xx_spi_dma_transfer_complete(drv_data, false);
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return IRQ_HANDLED;
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}
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} while (drv_data->write(drv_data));
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if (drv_data->read(drv_data)) {
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pxa2xx_spi_dma_transfer_complete(drv_data, false);
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return IRQ_HANDLED;
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}
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return IRQ_HANDLED;
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}
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int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
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{
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const struct chip_data *chip = drv_data->cur_chip;
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void *lpss_dma = drv_data->dma_priv;
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enum lpss_dma_buswidth width;
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enum lpss_dma_msize burstsize;
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u32 trail_bytes;
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switch (drv_data->n_bytes) {
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case 1:
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width = LPSS_DMA_BUSWIDTH_1_BYTE;
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break;
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case 2:
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width = LPSS_DMA_BUSWIDTH_2_BYTES;
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break;
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case 4:
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default:
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width = LPSS_DMA_BUSWIDTH_4_BYTES;
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break;
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}
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switch (dma_burst) {
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case 8:
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burstsize = LPSS_DMA_MSIZE_8;
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break;
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case 16:
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default:
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burstsize = LPSS_DMA_MSIZE_16;
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break;
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}
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trail_bytes = drv_data->len % (chip->dma_burst_size * drv_data->n_bytes);
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drv_data->tx_map_len = drv_data->rx_map_len = drv_data->len - trail_bytes;
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lpss_dma_set_buswidth(lpss_dma, width);
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lpss_dma_set_burstsize(lpss_dma, burstsize);
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return 0;
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}
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void pxa2xx_spi_dma_start(struct driver_data *drv_data)
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{
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void *lpss_dma = drv_data->dma_priv;
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lpss_dma_start_tx(lpss_dma, drv_data->tx, drv_data->tx_map_len);
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lpss_dma_start_rx(lpss_dma, drv_data->rx, drv_data->rx_map_len);
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atomic_set(&drv_data->dma_running, 1);
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}
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static struct lpss_dma_info pxa2xx_dma_info = {
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.dma_buswidth = LPSS_DMA_BUSWIDTH_1_BYTE,
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.dma_burstsize = LPSS_DMA_MSIZE_8,
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.rx_callback = pxa2xx_spi_dma_callback,
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};
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#define LPSS_IDMA_OFFSET 0x800
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int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
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{
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struct ssp_device *ssp = drv_data->ssp;
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struct lpss_dma_info *dma_info = &pxa2xx_dma_info;
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int ret;
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drv_data->dummy = lpss_dma_alloc(SZ_4K);
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if (!drv_data->dummy)
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return -ENOMEM;
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/* setup lpss dma */
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dma_info->pdev = &drv_data->pdev->dev;
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dma_info->membase = drv_data->ioaddr + LPSS_IDMA_OFFSET;
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dma_info->irq = ssp->irq;
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snprintf(dma_info->name, sizeof(dma_info->name) - 1, "%s_%d", "pxa2xx-spi", ssp->port_id);
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dma_info->per_tx_addr = dma_info->per_rx_addr = drv_data->ssdr_physical;
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dma_info->callback_param = drv_data;
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/* get baytrail or cherrytrail lpss dma info */
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ret = lpss_get_controller_info(lpss_spi_dma, ssp->port_id - 1, dma_info);
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if (ret < 0)
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goto err;
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drv_data->dma_priv = lpss_dma_register(dma_info);
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if (!drv_data->dma_priv) {
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ret = -ENODEV;
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goto err;
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}
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return 0;
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err:
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lpss_dma_free(drv_data->dummy);
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return ret;
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}
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void pxa2xx_spi_dma_release(struct driver_data *drv_data)
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{
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void *lpss_dma = drv_data->dma_priv;
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lpss_dma_free(drv_data->dummy);
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lpss_dma_unregister(lpss_dma);
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}
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void pxa2xx_spi_dma_suspend(struct driver_data *drv_data)
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{
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}
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void pxa2xx_spi_dma_resume(struct driver_data *drv_data)
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{
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}
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int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
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struct spi_device *spi,
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u8 bits_per_word, u32 *burst_code,
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u32 *threshold)
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{
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struct pxa2xx_spi_chip *chip_info = spi->controller_data;
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/*
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* If the DMA burst size is given in chip_info we use that,
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* otherwise we use the default. Also we use the default FIFO
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* thresholds for now.
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*/
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*burst_code = chip_info ? chip_info->dma_burst_size : 8;
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*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
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| SSCR1_TxTresh(TX_THRESH_DFLT);
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chip->lpss_rx_threshold = SSIRF_RxThresh(*burst_code);
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return 0;
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}
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