339 lines
12 KiB
C
339 lines
12 KiB
C
/*COPYRIGHT**
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Copyright (C) 2012-2014 Intel Corporation. All Rights Reserved.
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This file is part of SEP Development Kit
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SEP Development Kit is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation.
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SEP Development Kit is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with SEP Development Kit; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software
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library without restriction. Specifically, if other files instantiate
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templates or use macros or inline functions from this file, or you compile
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this file and link it with other files to produce an executable, this
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file does not by itself cause the resulting executable to be covered by
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the GNU General Public License. This exception does not however
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invalidate any other reasons why the executable file might be covered by
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the GNU General Public License.
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**COPYRIGHT*/
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#include "lwpmudrv_defines.h"
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#include <linux/version.h>
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#include <linux/wait.h>
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#include <linux/fs.h>
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#include "lwpmudrv_types.h"
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#include "rise_errors.h"
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#include "lwpmudrv_ecb.h"
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#include "lwpmudrv_struct.h"
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#include "lwpmudrv.h"
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#include "utility.h"
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#include "control.h"
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#include "output.h"
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#include "hsw_unc_power.h"
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#include "snb_unc_power.h"
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#include "avt_unc_power.h"
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#include "ecb_iterators.h"
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#include "unc_common.h"
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extern U64 *read_unc_ctr_info;
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/******************************************************************************************
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* @fn static VOID unc_power_snb_Write_PMU(VOID*)
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*
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* @brief No registers to write and setup the accumalators with initial values
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*
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* @return None
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*
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* <I>Special Notes:</I>
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******************************************************************************************/
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static VOID
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unc_power_snb_Write_PMU (
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VOID *param
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)
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{
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U32 dev_idx = *((U32*)param);
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U64 tmp_value = 0;
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U32 j;
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U32 event_id = 0;
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FOR_EACH_REG_ENTRY_UNC(pecb, dev_idx, i) {
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for ( j = 0; j < (U32)GLOBAL_STATE_num_cpus(driver_state); j++) {
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tmp_value = SYS_Read_MSR(ECB_entries_reg_id(pecb,i)) & SNB_POWER_MSR_DATA_MASK;
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LWPMU_DEVICE_prev_val_per_thread(&devices[dev_idx])[j][event_id + 1] = tmp_value; // need to account for group id
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}
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// Initialize counter_mask for accumulators
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if (LWPMU_DEVICE_counter_mask(&devices[dev_idx]) == 0) {
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LWPMU_DEVICE_counter_mask(&devices[dev_idx]) = (U64)ECB_entries_max_bits(pecb,i);
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}
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} END_FOR_EACH_REG_ENTRY_UNC;
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return;
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}
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/* ------------------------------------------------------------------------- */
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/*!
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* @fn unc_power_snb_Read_Counts(param, id)
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*
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* @param param The read thread node to process
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* @param id The event id for the which the sample is generated
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*
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* @return None No return needed
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*
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* @brief Read the Uncore count data and store into the buffer param;
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* Uncore PMU does not support sampling, i.e. ignore the id parameter.
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*/
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static VOID
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unc_power_snb_Read_Counts (
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PVOID param,
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U32 id
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)
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{
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UNC_COMMON_MSR_Read_Counts_With_Mask(param, id, SNB_POWER_MSR_DATA_MASK);
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return;
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}
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/* ------------------------------------------------------------------------- */
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/*!
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* @fn unc_power_hsw_Read_Counts(param, id)
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*
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* @param param The read thread node to process
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*
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* @return None No return needed
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*
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* @brief Read the Uncore count data and store into the buffer param;
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* Uncore PMU does not support sampling, i.e. ignore the id parameter.
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*/
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static VOID
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unc_power_hsw_Read_Counts (
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PVOID param,
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U32 id
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)
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{
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UNC_COMMON_MSR_Read_Counts_With_Mask(param, id, HASWELL_POWER_MSR_DATA_MASK);
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return;
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}
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/* ------------------------------------------------------------------------- */
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/*!
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* @fn unc_power_hsw_Read_PMU_Data(param)
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*
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* @param param The read thread node to process
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* @param id The event id for the which the sample is generated
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*
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* @return None No return needed
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*
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* @brief Read the Uncore count data and store into the buffer param;
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* Uncore PMU does not support sampling, i.e. ignore the id parameter.
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*/
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static VOID
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unc_power_hsw_Read_PMU_Data (
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PVOID param
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)
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{
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S32 j;
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U64 *buffer = read_unc_ctr_info;
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U32 dev_idx = *((U32*)param);
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U32 start_index;
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DRV_CONFIG pcfg_unc;
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U32 this_cpu = CONTROL_THIS_CPU();
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CPU_STATE pcpu = &pcb[this_cpu];
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U32 num_cpus = GLOBAL_STATE_num_cpus(driver_state);
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U32 thread_event_count = 0;
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pcfg_unc = (DRV_CONFIG)LWPMU_DEVICE_pcfg(&devices[dev_idx]);
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start_index = DRV_CONFIG_emon_unc_offset(pcfg_unc, 0);
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FOR_EACH_DATA_REG_UNC(pecb, dev_idx, i) {
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if (ECB_entries_event_scope(pecb,i) == PACKAGE_EVENT) {
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j = start_index + thread_event_count*(num_cpus-1) + ECB_entries_group_index(pecb,i) + ECB_entries_emon_event_id_index_local(pecb,i);
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if (!CPU_STATE_socket_master(pcpu)) {
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continue;
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}
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}
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else {
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j = start_index + this_cpu + thread_event_count*(num_cpus-1) + ECB_entries_group_index(pecb,i) + ECB_entries_emon_event_id_index_local(pecb,i);
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thread_event_count++;
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}
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buffer[j] = SYS_Read_MSR(ECB_entries_reg_id(pecb,i));
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} END_FOR_EACH_DATA_REG_UNC;
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return;
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}
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/* ------------------------------------------------------------------------- */
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/*!
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* @fn unc_power_avt_Read_Counts(param, id)
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*
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* @param param The read thread node to process
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* @param id The event id for the which the sample is generated
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*
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* @return None No return needed
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*
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* @brief Read the Uncore count data and store into the buffer param;
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* Uncore PMU does not support sampling, i.e. ignore the id parameter.
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*/
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static VOID
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unc_power_avt_Read_Counts (
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PVOID param,
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U32 id
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)
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{
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UNC_COMMON_MSR_Read_Counts_With_Mask(param, id, 0xFFFFFFFFFFFFFFFFULL);
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return;
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}
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/* ------------------------------------------------------------------------- */
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/*!
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* @fn unc_power_avt_Read_PMU_Data(param)
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*
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* @param param The read thread node to process
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*
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* @return None No return needed
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*
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* @brief Read the Uncore count data and store into the buffer param;
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* Uncore PMU does not support sampling, i.e. ignore the id parameter.
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*/
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static VOID
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unc_power_avt_Read_PMU_Data (
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PVOID param
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)
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{
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S32 j;
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U64 *buffer = read_unc_ctr_info;
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U32 dev_idx = *((U32*)param);
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U32 start_index;
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DRV_CONFIG pcfg_unc;
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U32 this_cpu = CONTROL_THIS_CPU();
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CPU_STATE pcpu = &pcb[this_cpu];
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U32 num_cpus = GLOBAL_STATE_num_cpus(driver_state);
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U32 cur_grp = LWPMU_DEVICE_cur_group(&devices[(dev_idx)]);
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U32 package_event_count = 0;
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U32 thread_event_count = 0;
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U32 module_event_count = 0;
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pcfg_unc = (DRV_CONFIG)LWPMU_DEVICE_pcfg(&devices[dev_idx]);
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start_index = DRV_CONFIG_emon_unc_offset(pcfg_unc, cur_grp);
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FOR_EACH_DATA_REG_UNC(pecb, dev_idx, i) {
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j = start_index + ECB_entries_group_index(pecb,i) +
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package_event_count*num_packages +
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module_event_count*(GLOBAL_STATE_num_modules(driver_state)) +
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thread_event_count*num_cpus ;
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if (ECB_entries_event_scope(pecb,i) == PACKAGE_EVENT) {
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j = j + core_to_package_map[this_cpu];
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package_event_count++;
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if (!CPU_STATE_socket_master(pcpu)) {
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continue;
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}
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}
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else if (ECB_entries_event_scope(pecb,i) == MODULE_EVENT) {
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j = j + CPU_STATE_cpu_module_num(pcpu);
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module_event_count++;
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if (!CPU_STATE_cpu_module_master(pcpu)) {
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continue;
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}
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}
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else {
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j = j + this_cpu;
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thread_event_count++;
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}
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buffer[j] = SYS_Read_MSR(ECB_entries_reg_id(pecb,i));
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//SEP_PRINT_DEBUG("cpu=%d j=%d mec=%d mid=%d tec=%d i=%d gi=%d ei=%d count=%llu\n", this_cpu, j, module_event_count, CPU_STATE_cpu_module_num(pcpu), thread_event_count, i, ECB_entries_group_index(pecb,i), ECB_entries_emon_event_id_index_local(pecb,i), buffer[j]);
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} END_FOR_EACH_DATA_REG_UNC;
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return;
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}
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/*
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* Initialize the dispatch table
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*/
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DISPATCH_NODE snb_power_dispatch =
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{
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NULL, // initialize
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NULL, // destroy
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unc_power_snb_Write_PMU, // write
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NULL, // freeze
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NULL, // restart
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NULL, // read
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NULL, // check for overflow
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NULL, // swap group
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NULL, // read lbrs
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NULL, // cleanup
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NULL, // hw errata
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NULL, // read power
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NULL, // check overflow errata
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unc_power_snb_Read_Counts, // read counts
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NULL, // check overflow gp errata
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NULL, // read_ro
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NULL, // platform info
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NULL,
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NULL // scan for uncore
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};
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/*
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* Initialize the dispatch table
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*/
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DISPATCH_NODE haswell_power_dispatch =
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{
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NULL, // initialize
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NULL, // destroy
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UNC_COMMON_Dummy_Func, // write
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NULL, // freeze
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NULL, // restart
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unc_power_hsw_Read_PMU_Data, // read
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NULL, // check for overflow
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NULL, // swap group
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NULL, // read lbrs
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NULL, // cleanup
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NULL, // hw errata
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NULL, // read power
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NULL, // check overflow errata
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unc_power_hsw_Read_Counts, // read counts
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NULL, // check overflow gp errata
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NULL, // read_ro
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NULL, // platform info
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NULL,
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NULL // scan for uncore
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};
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/*
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* Initialize the dispatch table
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*/
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DISPATCH_NODE avoton_power_dispatch =
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{
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NULL, // initialize
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NULL, // destroy
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UNC_COMMON_Dummy_Func, // write
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NULL, // freeze
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NULL, // restart
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unc_power_avt_Read_PMU_Data, // read
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NULL, // check for overflow
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NULL, // swap group
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NULL, // read lbrs
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NULL, // cleanup
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NULL, // hw errata
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NULL, // read power
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NULL, // check overflow errata
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unc_power_avt_Read_Counts, // read counts
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NULL, // check overflow gp errata
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NULL, // platform info
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NULL,
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NULL // scan for uncore
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};
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