Add debug trace
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a785d2eb12
commit
feeae16d5b
11
dsim.c
11
dsim.c
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@ -19,6 +19,7 @@ uint16_t lit; /* temporary storage for literal operands */
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bool skip_next;
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uint64_t ticks;
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bool running;
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bool trace;
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bool intq_en;
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#define MAX_INTQ_SIZE 256
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uint16_t intq[MAX_INTQ_SIZE];
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@ -75,6 +76,7 @@ void reset()
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skip_next = false;
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ticks = 0;
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trace = false;
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running = true;
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}
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@ -100,6 +102,12 @@ void debug_irqh()
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case 0x0002:
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dump_ram(ry, rx);
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break;
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case 0x0004:
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trace = false;
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break;
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case 0x0005:
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trace = true;
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break;
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case 0xffff:
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rx = EMU_ID;
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ry = EMU_VER;
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@ -496,6 +504,9 @@ void next()
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}
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}
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if (trace)
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dumpregs();
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ir = ram[rpc++];
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opcode = ir & 0x001f;
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